MEMORY存储芯片TMS320DM350ZWK中文规格书

SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

3DeviceOverview

3.1

DeviceCharacteristics

Table3-1providesanoverviewoftheC6745/6747lowpowerdigitalsignalprocessor.Thetableshowssignificantfeaturesofthedevice,includingthecapacityofon-chipRAM,peripherals,andthepackagetypewithpincount.

Table3-1.CharacteristicsoftheC6745/C6747Processor

HARDWAREFEATURES

EMIFBEMIFA

FlashCardInterfaceEDMA3TimersUARTSPII2C

MultichannelAudioSerialPort[McASP]

Peripherals

Notallperipheralspinsareavailableatthe

eHRPWMsametime(formore

detail,seetheDeviceeCAPConfigurationssection).

eQEP

UHPI

USB2.0(USB0)USB1.1(USB1)General-PurposeInput/OutputPortLCDControllerRTC

PRUSubsystem(PRUSS)Size(Bytes)

320KBRAM

--10/100EthernetMACwithManagementDataI/O

C6745

16bit,upto128MBSDRAMAsynchronous(8-bitbuswidth)RAM,

Flash,NOR,NAND

C6747

16/32bit,upto256MBSDRAMAsynchronous(8/16-bitbuswidth)RAM,Flash,16bitupto128MBSDRAM,NOR,

NAND

MMCandSDcardssupported.

32independentchannels,8QDMAchannels,2Transfercontrollers

264-BitGeneralPurpose(eachconfigurableas2separate32-bittimers,1configurable

asWatchDog)

3(onewithRTSandCTSflowcontrol)2(eachwithonehardwarechipselect)

2(bothMaster/Slave)

2(eachwithtransmit/receive,FIFObuffer,

16/9serializers)

3(eachwithtransmit/receive,FIFObuffer,

16/9serializers)

1(RMIIInterface)

6SingleEdge,6DualEdgeSymmetric,or3DualEdgeAsymmetricOutputs

332-bitcaptureinputsor332-bitauxiliaryPWMoutputs

232-bitQEPchannelswith4inputs/channel-FullSpeedHostOrDevicewithOn-Chip

PHY

-1(16-bitmultiplexedaddress/data)High-SpeedOTGControllerwithon-chip

OTGPHYFull-SpeedOHCI(ashost)withon-chip

PHY

8banksof16-bit

1

1(32KHzoscillatorandseperatepowertrail.Providestimeanddatetrackingand

alarmcapability.)

2ProgrammablePRUCores

448KBRAM

On-ChipMemory

Organization

DSP

32KBL1Program(L1P)/Cache(upto32KB)32KBL1Data(L1D)/Cache(upto32KB)256KBUnifiedMappedRAM/Cache(L2)

DSPMemoriescanbemadeaccessibletoEDMA3,andotherperipherals.

ADDITIONALMEMORY

128KBRAM

0x14000x0000

-C674xCPUID+CPURevID

C674xMegamoduleRevision

ControlStatusRegister(CSR.[31:16])RevisionIDRegister(MM_REVID[15:0])

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TMS320C6745,TMS320C6747

SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

3.3DSPSubsystem

TheDSPSubsystemincludesthefollowingfeatures:•C674xDSPCPU

•32KBL1Program(L1P)/Cache(upto32KB)•32KBL1Data(L1D)/Cache(upto32KB)•256KBUnifiedMappedRAM/Cache(L2)

•BootROM(cannotbeusedforapplicationcode)•Littleendian

32K BytesL1PRAM/Cache256256K BytesL2 RAMBoot ROM256256Cache ControlMemory ProtectBandwidth Mgmt256Instruction FetchC674xFixed/Floating Point CPURegisterFileA64Bandwidth MgmtMemory ProtectCache ControlL1DRegisterFile B64256L1P256Cache ControlMemory ProtectBandwidth MgmtL2256256Power DownInterruptControllerIDMA256CFGEMCMDMA646464SDMA6432ConfigurationPeripheralsBus8 x 3232K BytesL1D RAM/CacheHighPerformanceSwitch FabricFigure3-1.C674xMegamoduleBlockDiagram

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