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SUMMARY
SHARC ProcessorsADSP-21367/ADSP-21368/ADSP-21369Code compatible with all other members of the SHARC familyThe ADSP-21367/ADSP-21368/ADSP-21369 are available with a 333 MHz core instruction rate with unique audiocen-tric peripherals such as the digital audio interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page56.
®High performance 32-bit/40-bit floating point processor optimized for high performance audio processingSingle-instruction, multiple-data (SIMD) computational architecture
On-chip memory—2M bit of on-chip SRAM and 6M bit of on-chip mask programmable ROM
COREPROCESSORTIMERINSTRUCTIONCACHE32 ×48-BITJTAGTEST&EMULATION4BLOCKOFON-CHIPMEMORY2MBITRAM6MBITROMFLAGS4-15PWM32DATACONTROLPINSDAG18×4×32DAG28×4×32PROGRAMSEQUENCERADDRDATAEXTERNALPORTSDRAMCONTROLLER718PMADDRESSBUSDMADDRESSBUS3232PMDATABUS64ASYNCHRONOUSMEMORYINTERFACESHAREDMEMORYINTERFACEIOA(24)IOD(32)3CONTROL24ADDRESS8DMDATABUS64PROCESSINGELEMENT(PEX)PROCESSINGELEMENT(PEY)PXREGISTERIOPREGISTER(MEMORYMAPPED)CONTROL,STATUS,&DATABUFFERSDMACONTROLLER34CHANNELSMEMORY-TO-MEMORYDMA(2)DAIROUTINGUNITSERIALPORTS(8)INPUTDATAPORT/PDAPDAIPINSSPIPORT(2)TWOWIREINTERFACEDPIPINS4DPIROUTINGUNITPRECISIONCLOCKGENERATORS(4)GPIOFLAGS/IRQ/TIMEXPSRC(8CHANNELS)SPDIF(Rx/Tx)UART(2)STIMERS(3)DIGITALAUDIOINTERFACE20DIGITALPERIPHERALINTERFACEI/OPROCESSOR14Figure 1.Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use.Specifications subject to change without notice. No license is granted by implicationor otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective companies.
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ADSP-21367/ADSP-21368/ADSP-21369
KEY FEATURES—PROCESSOR CORE
At 333 MHz (3 ns) core instruction rate, the processors per-form 2 GFLOPS/666 MMACS
2M bit on-chip, SRAM (0.75M bit in blocks 0 and 1, and
0.25M bit in blocks 2 and 3) for simultaneous access by the core processor and DMA
6M bit on-chip, mask-programmable ROM (3M bit in block 0 and 3M bit in block 1)
Dual data address generators (DAGs) with modulo and bit-reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-ing efficient program sequencing
Single-instruction, multiple-data (SIMD) architecture provides:
Two computational processing elementsConcurrent execution
Code compatibility with other SHARC family members at the assembly level
Parallelism in buses and computational units allows: single cycle executions (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch
Transfers between memory and core at a sustained
6.4G bytes/s bandwidth at 333 MHz core instruction rate
Digital audio interface (DAI) includes eight serial ports, four precision clock generators, an input data port, an S/PDIF transceiver, an 8-channel asynchronous sample rate con-verter, and a signal routing unit
Digital peripheral interface (DPI) includes three timers, two UARTs, two SPI ports, and a two wire interface portOutputs of PCG's C and D can be driven on to DPI pinsEight dual data line serial ports that operate at up to
50M bits/s on each data line—each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair
TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110
Up to 16 TDM stream support, each with 128 channels per frame
Companding selection on a per channel basis in TDM modeInput data port, configurable as eight channels of serial data or seven channels of serial data and up to a 20-bit wide parallel data channel
Signal routing unit provides configurable and flexible con-nections between all DAI/DPI components2 muxed flag/IRQ lines1 muxed flag/timer expired line /MS pin1 muxed flag/IRQ /MS pin INPUT/OUTPUT FEATURES
DMA controller supports:
34 zero-overhead DMA channels for transfers between internal memory and a variety of peripherals
32-bit DMA transfers at peripheral clock speed, in parallel with full-speed processor execution
32-bit wide external port provides glueless connection to both synchronous (SDRAM) and asynchronous memory devices
Programmable wait state options: 2 SCLK to 31 SCLK cyclesDelay-line DMA engine maintains circular buffers in exter-nal memory with tap/offset-based reads
SDRAM accesses at 133 MHz and asynchronous accesses at 66 MHz
Shared-memory support allows multiple DSPs to automat-ically arbitrate for the bus and gluelessly access a common memory device
Shared memory interface (ADSP-21368 only) support provides:
Glueless connection for scalable DSP multiprocessingarchitecture
Distributed on-chip bus arbitration for parallel bus
Connect of up to four ADSP-21368 processors and global memory
Four memory select lines allow multiple external memory devices
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter sup-ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standardsLeft-justified, I2S, or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter)
Four independent asynchronous sample rate converters (SRC). Each converter has separate serial input and output ports, a de-emphasis filter providing up to –140 dB SNR performance, stereo sample rate converter (SRC) and sup-ports left-justified, I2S, TDM, and right-justified modes and 24, 20, 18, and 16 audio data word lengthsPulse-width modulation provides:
16 PWM outputs configured as four groups of four outputs supports center-aligned or edge-aligned PWM waveformsROM-based security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit access under program control to sensitive codePLL has a wide variety of software and hardware multi-plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V or 1.3 V core
Available in 256-ball SBGA and 208-lead MQFP packages (see Ordering Guide on Page56)
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TABLE OF CONTENTSSummary ................................................................1Key Features—Processor Core ..................................2Input/Output Features ............................................2Dedicated Audio Components ..................................2General Description ..................................................4Core Architecture ..................................................4Memory Architecture .............................................5External Memory ...................................................5Input/Output Features ............................................7System Design .......................................................9Development Tools ..............................................10Additional Information .........................................11Pin Function Descriptions ........................................12Data Modes ........................................................15Boot Modes ........................................................15Core Instruction Rate to CLKIN Ratio Modes .............15Specifications .........................................................16Operating Conditions ...........................................16Electrical Characteristics ........................................17Package Information ............................................18Maximum Power Dissipation .................................18Absolute Maximum Ratings ...................................18ESD Sensitivity ....................................................18Timing Specifications ...........................................19Output Drive Currents ..........................................47Test Conditions ...................................................47Capacitive Loading ...............................................47Thermal Characteristics ........................................48256-Ball SBGA Pinout ..............................................49208-Lead MQFP Pinout ............................................52Package Dimensions ................................................54Surface-Mount Design ..........................................55Ordering Guide ......................................................56
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GENERAL DESCRIPTIONThe ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-sors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These pro-cessors are source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating point processors optimized for high performance automotive audio applications with its large on-chip SRAM, and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI).
As shown in the functional block diagram onPage1, the
processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21367/ADSP-21368/
ADSP-21369 processors achieve an instruction cycle time of up to 3.0 ns at 333 MHz. With its SIMD computational hardware, the processors can perform two GFLOPS running at 333 MHz. Table1 shows performance benchmarks for these devices.Table 1.Processor Benchmarks (at 333 MHz)
Speed
Benchmark Algorithm(at 333 MHz)1024 Point Complex FFT (Radix 4, with reversal)27.9 μsFIR Filter (per tap)11.5 ns IIR Filter (per biquad)16.0 ns Matrix Multiply (pipelined)[3×3] × [3×1]13.5 ns[4×4] × [4×1]23.9 nsDivide (y/×)10.5 ns Inverse Square Root16.3 ns
1 •On-chipmask-programmable ROM (6M bit)•JTAG test access port
The block diagram of the ADSP-21368 onPage1 also illustrates
the following architectural features:•DMA controller
•Eight full-duplex serial ports
•Digital audio interface that includes four precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, eight channels asynchronous sample rate converters, eight serial ports, eight serial interfaces, a 16-bit parallel input port (PDAP), a flexible signal routing unit (DAI SRU).
•Digital peripheral interface that includes three timers, an I2C® interface, two UARTs, two serial peripheral interfaces (SPI), and a flexible signal routing unit (DPI SRU).
CORE ARCHITECTURE
The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-ble at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21367/ADSP-21368/
ADSP-21369 share architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as detailed in the following sections.
SIMD Computational Engine
The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing ele-ments, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band-width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.
Assumes two files in multichannel SIMD mode.
The ADSP-21367/ADSP-21368/ADSP-21369 continues
SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21368 onPage1, illustrates the following architectural features:
•Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file•Data address generators (DAG1, DAG2)•Program sequencer with instruction cache
•PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core pro-cessor cycle
•Three programmable interval timers with PWM genera-tion, PWM capture/pulse width measurement, and external event counter capabilities•On-chipSRAM(2Mbit)
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Independent, Parallel Computation Units
Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera-tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel
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ALU and multiplier operations occur in both processing ele-ments. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats.
MEMORY ARCHITECTURE
The ADSP-21367/ADSP-21368/ADSP-21369 processors add the following architectural features to the SIMD SHARC family core.
Data Register File
A general-purpose data register file is contained in each pro-cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har-vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.
On-Chip Memory
The processors contain two megabits of internal RAM and six megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data stor-age (see Table2 on Page6). Each memory block supports
single-cycle, independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle.
The SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is per-formed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.
Single-Cycle Fetch of Instruction and Four OperandsThe ADSP-21367/ADSP-21368/ADSP-21369 feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure1 on Page1). With separate program and data memory buses and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.
Instruction Cache
The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.
Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
The ADSP-21367/ADSP-21368/ADSP-21369 have two data address generators (DAGs). The DAGs are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second-ary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and sim-plify implementation. Circular buffers can start and end at any memory location.
EXTERNAL MEMORY
The external port provides a high performance, glueless inter-face to a wide variety of industry-standard memory devices. The 32-bit wide bus may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs (Dual Inline Memory Module), while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. NonSDRAM external memory address space is shown in Table3.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the
ADSP-21367/ADSP-21368/ADSP-21369 can conditionally exe-cute a multiply, an add, and a subtract in both processing
elements while branching and fetching up to four 32-bit values from memory—all in a single instruction.
SDRAM Controller
The SDRAM controller provides an interface of up to four sepa-rate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 16Mbytes and 128Mbytes of memory. SDRAM external memory address space is shown in Table4.
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Table 2.Internal Memory Space1IOP Registers 0x0000 0000–0x0003 FFFFLong Word (64 Bits)BLOCK 0 ROM (Reserved)0x0004 0000–0x0004 BFFF Reserved
0x0004 F000–0x0004 FFFF BLOCK 0 SRAM
0x0004 C000–0x0004 EFFF BLOCK 1 ROM (Reserved)0x0005 0000–0x0005 BFFFReserved
0x0005 F000–0x0005 FFFFBLOCK 1 SRAM
0x0005 C000–0x0005 EFFF BLOCK 2 SRAM
0x0006 0000–0x0006 0FFFReserved
0x0006 1000– 0x0006 FFFF BLOCK 3 SRAM
0x0007 0000–0x0007 0FFFReserved
0x0007 1000–0x0007 FFFF
1Extended Precision Normal or Instruction Word (48 Bits)BLOCK 0 ROM (Reserved)0x0008 0000–0x0008 FFFFReserved
0x0009 4000–0x0009 FFFFBLOCK 0 SRAM
0x0009 0000–0x0009 3FFFBLOCK 1 ROM (Reserved)0x000A 0000–0x000A FFFFReserved
0x000B 4000–0x000B FFFFBLOCK 1 SRAM
0x000B 0000–0x000B 3FFFBLOCK 2 SRAM
0x000C 0000–0x000C 1554Reserved
0x000C 1555–0x000C 3FFFBLOCK 3 SRAM
0x000E 0000–0x000E 1554Reserved
0x000E 1555–0x000F FFFF
Normal Word (32 Bits)BLOCK 0 ROM (Reserved)0x0008 0000–0x0009 7FFFReserved
0x0009 E000–0x0009 FFFFBLOCK 0 SRAM
0x0009 8000–0x0009 DFFFBLOCK 1 ROM (Reserved)0x000A 0000–0x000B 7FFFReserved
0x000B E000–0x000B FFFFBLOCK 1 SRAM
0x000B 8000–0x000B DFFFBLOCK 2 SRAM
0x000C 0000–0x000C 1FFFReserved
0x000C 2000–0x000D FFFFBLOCK 3 SRAM
0x000E 0000–0x000E 1FFFReserved
0x000E 2000–0x000F FFFF
Short Word (16 Bits)BLOCK 0 ROM (Reserved)0x0010 0000–0x0012 FFFFReserved
0x0013 C000–0x0013 FFFFBLOCK 0 SRAM
0x0013 0000–0x0013 BFFFBLOCK 1 ROM (Reserved)0x0014 0000–0x0016 FFFFReserved
0x0017 C000–0x0017 FFFFBLOCK 1 SRAM
0x0017 0000–0x0017 BFFFBLOCK 2 SRAM
0x0018 0000–0x0018 3FFFReserved
0x0018 4000–0x001B FFFFBLOCK 3 SRAM
0x001C 0000–0x001C 3FFFReserved
0x001C 4000–0x001F FFFF
The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.
The controller maintains all of the memory banks as a contigu-ous address space so that the processor sees this as a single address space, even if different size devices are used in the different banks.
A set of programmable timing parameters is available to config-ure the SDRAM banks to support slower memory devices. The memory banks can be configured as either 32 bits wide for max-imum performance and bandwidth or 16 bits wide for minimum device count and lower system cost.
The SDRAM controller address, data, clock, and control pins can drive loads up to 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF.Table 3.External Memory for NonSDRAM Addresses
BankBank 0Bank 1Bank 2Bank 3
Size in Words14M16M16M16M
Address Range
0x0020 0000 – 0x00FF FFFF0x0400 0000 – 0x04FF FFFF0x0800 0000 – 0x08FF FFFF0x0C00 0000 – 0x0CFF FFFF
Table 4.External Memory for SDRAM Addresses
BankBank 0Bank 1Bank 2Bank 3
Size in Words62M64M64M64M
Address Range
0x0020 0000 – 0x03FF FFFF0x0400 0000 – 0x07FF FFFF0x0800 0000 – 0x0BFF FFFF0x0C00 0000 – 0x0FFF FFFF
Asynchronous Controller
The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-ferent timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory con-trol lines. Bank 0 occupies a 14M word window and banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The banks can also be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to high performance or to low cost and power.
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The asynchronous memory controller is capable of a maximum throughput of 264M bytes/s using a 66 MHz external bus speed. Other features include 8-bit to 32-bit and 16-bit to 32-bit pack-ing and unpacking, booting from bank select 1, and support for delay line DMA.
the SPI interface, two for the external port, and two for
memory-to-memory transfers. Programs can be downloaded to the processors using DMA transfers. Other DMA features include interrupt generation upon completion of DMA trans-fers, and DMA chaining for automatic linked DMA transfers. Delay Line DMA
The ADSP-21367/ADSP-21368/ADSP-21369 processors pro-vide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (in external memory, SRAM, or SDRAM) with limited core interaction.
Shared External Memory
The ADSP-21368 processor supports connecting to common
shared external memory with other ADSP-21368 processors to create shared external bus processor systems. This support includes:
•Distributed, on-chip arbitration for the shared external bus•Fixed and rotating priority bus arbitration•Bus time-out logic•Bus lock
Multiple processors can share the external bus with no addi-tional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to four processors.
Bus arbitration is accomplished through the BR1-4 signals and the priority scheme for bus arbitration is determined by the set-ting of the RPBA pin. Table5 on Page12 provides descriptions of the pins used in multiprocessor systems.
Digital Audio and Digital Peripheral Interfaces (DAI/DPI)The digital audio and digital periphal interfaces (DAI and DPI) provide the ability to connect various peripherals to any of the DSP’s DAI or DPI pins (DAI_P20–1 and DPI_P14–1).Programs make these connections using the signal routing units (SRU1 and SRU2), shown in Figure1.
The SRUs are matrix routing units (or group of multiplexers) that enable the peripherals provided by the DAI and DPI to be interconnected under software control. This allows easy use of the associated peripherals for a much wider variety of applica-tions by using a larger set of algorithms than is possible with nonconfigurable signal paths.
The DAI and DPI also include eight serial ports, an S/PDIF receiver/transmitter, four precision clock generators (PCG), eight channels of synchronous sample rate converters, and an input data port (IDP). The IDP provides an additional input path to the processor core, configurable as either eight channels of I2S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the proces-sor’s serial ports.
For complete information on using the DAI and DPI, see the ADSP-21368 SHARC Processor Hardware Reference.
INPUT/OUTPUT FEATURES
The I/O processor provides 34 channels of DMA, as well as an extensive set of peripherals. These include a 20-pin digital audio interface which controls:•Eight serial ports
•S/PDIF receiver/transmitter•Four precision clock generators•Four stereo sample rate converters
•Internal data port/parallel data acquisition port
The processors also contain a 14-pin digital peripheral interface which controls:
•Three general-purpose timers•Two serial peripheral interfaces
•Twouniversalasynchronous receiver/transmitters (UARTs)
•A two-wire interface (I2C-compatible)
Serial Ports
The processors feature eight synchronous serial ports (SPORTs) that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel.
Serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight SPORTS are enabled, or eight full duplex TDM streams of 128 channels per frame.
The serial ports operate at a maximum data rate of 50M bits/s. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit sig-nals while the other SPORT provides the two receive signals. The frame sync and clock are shared.
DMA Controller
The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously exe-cuting its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the UART. Thirty-four channels of DMA are available on the ADSP-21367/ADSP-21368/ADSP-21369—16 via the serial ports, eight via the input data port, four for the UARTs, two for
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Serial ports operate in five modes:•Standard DSP serial mode
•Multichannel(TDM) mode with support for packed I2S mode•I2S mode
2S mode•PackedI
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), two universal asynchro-nous receiver-transmitters (UARTs), a two-wire interface (TWI), 12 flags, and three general-purpose timers.
Serial Peripheral (Compatible) Interface
The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchro-nous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21367/
ADSP-21368/ADSP-21369 SPI-compatible peripheral imple-mentation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.
•Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var-ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface com-monly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S chan-nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be inter-nally or externally generated.
The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for
example, frame syncs that arrive while the transmission/recep-tion of the previous word is occurring). All the serial ports also share one dedicated error interrupt.
UART Port
The processors provide a full-duplex universal asynchronous
receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simpli-fied UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capa-bility using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface stan-dard. The UART port also includes support for five data bits to eightdata bits, one stop bit or twostop bits, and none, even, or odd parity. The UART port supports two modes of operation:•PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.•DMA (direct memory access) – The DMA controller trans-fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.The UART port’s baud rate, serial data format, error code gen-eration and status, and interrupts are programmable:•Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second.
•Supporting data formats from 7 bits to 12bits per frame.•Both transmit and receive operations can be configured to generate maskable interrupts to the processor.
Where the 16-bit UART_Divisor comes from the DLH register (most significant eight bits) and DLL register (least significant eightbits).
S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate ConverterThe S/PDIF receiver/transmitter has no separate DMA chan-nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits.The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers.
The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asyn-chronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to con-vert multichannel audio data without phase mismatches.
Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver.
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In conjunction with the general-purpose timer functions, auto-baud detection is supported.
midpoint of the PWM period. In this mode, it is possible to pro-duce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters.
Timers
The ADSP-21367/ADSP-21368/ADSP-21369 have a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes:
•Pulse waveform generation mode•Pulse width count/capture mode•External event watchdog mode
The core timer can be configured to use FLAG3 as a timer expired signal, and each general purpose timer has one bidirec-tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin-gle control and status register enables or disables all three general-purpose timers independently.
ROM-Based Security
The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu-rity feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the pro-cessor does not boot-load any external code, executing
exclusively from internal SRAM/ROM. Additionally, the pro-cessor is not freely accessible via the JTAG port. Instead, a
unique 64-bit key, which must be scanned in through the JTAG or test access port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.
SYSTEM DESIGN
The following sections provide an introduction to system design options and power supply issues.
Two-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features:•Simultaneous master and slave operation on multiple device systems with support for multimaster data arbitration
•Digital filtering and timed event processing•7-bit and 10-bit addressing
•100K bits/s and 400K bits/s data rates•Low interrupt rate
Program Booting
The internal memory of the processors can be booted up at sys-tem power-up from an 8-bit EPROM via the external port, an SPI master or slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins (see Table7 on Page15). Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM.
Power Supplies
The processors have separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS)
power supplies. The internal and analog supplies must meet the 1.3 V requirement for the 333 MHz device and 1.2 V for the 266 MHz device. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the same power supply.
Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is rec-ommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure2. (A recom-mended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure2 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to dig-ital ground (GND) at the chip.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave-forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non-paired mode (applicable to a single group of four PWM waveforms).
The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs.
The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the
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100nFVDDINT10nF1nFADSP-213xxAVDDdeveloper can identify bottlenecks in software quickly and effi-ciently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.
Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:
•View mixed C/C++ and assembly code (interleaved source and object information)•Insert breakpoints
•Set conditional breakpoints on registers, memory, andstacks
•Trace instruction execution
•Perform linear or statistical profiling of program execution•Fill, dump, and graphically plot the contents of memory•Perform source level debugging•Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC devel-opment tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:•Control how the development tools process inputs and generate outputs
•Maintain a one-to-one correspondence with the tool’s command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the mem-ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the gen-eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.VisualDSP++ Component Software Engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. The user can download components from the Web, drop them into the application, and publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.
HI-ZFERRITEBEADCHIPAVSSLOCATEALLCOMPONENTSCLOSETOAVDDANDAVSSPINSFigure 2.Analog Power (AVDD) Filter Circuit
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21367/ADSP-21368/ADSP-21369 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro-priate “Emulator Hardware User’s Guide.”
DEVELOPMENT TOOLS
The processors are supported with a complete set of CROSS-CORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21367/ADSP-21368/ADSP-21369.
The VisualDSP++ project management environment lets pro-grammers develop and debug an application. This environment includes an easy to use assembler (which is based on an alge-braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa-tion of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in com-plexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Sta-tistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the
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Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utiliza-tion in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. The expert linker is fully compatible with the existing linker def-inition file (LDF), allowing the developer to move between the graphical and textual environments.
In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard-ware tools include SHARC processor PC plug-in cards. Third-party software tools include DSP libraries, real-time operating systems, and block diagram designtools.
in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a stand-alone unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, non-intrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-21367/ADSP-21368/ADSP-21369 architecture and func-tionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-21368 SHARC Processor Hardware Reference and the ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference.
Designing an Emulator-Compatible DSP Board(Target)The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter-face—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal fea-tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and com-mands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter-mination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace withimprovements to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite® evaluation plat-forms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-sor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows
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PIN FUNCTION DESCRIPTIONSThe following symbols appear in the Type column of Table5: A = asynchronous, G = ground, I=input, O = output,
O/T = output three-state, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, (pd) = pull-down resistor, (pu) = pull-up resistor. Table 5.Pin List
State During/ After Reset (ID = 00x)Pulled high/driven lowPulled high/pulled highNameADDR23–0DATA31–0TypeO/T (pu)1I/O (pu)1DescriptionExternal Address. The processors output addresses for external memory and periph-erals on these pins. External Data. Data pins can be multiplexed to support external memory interface data (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_PDAP_CTL register, IDP Channel 0 scans the DATA31–8 pins for parallel input data.Digital Audio Interface. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric periph-eral inputs or outputs connected to the pin, and to the pin’s output enable. The configuration registers then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU provides the connection from the serial ports (8), the SRC module, the S/PDIF module, input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pull-ups can be disabled via the DAI_PIN_PULLUP register.Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output—so the pins used for I2C data and clock should be connected to logic level 0. Pull-ups can be disabled via the DPI_PIN_PULLUP register.Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. DAI _P20–1I/O with pro-grammable pu2Pulled high/ pulled highDPI _P14–1I/O with pro-grammable pu2Pulled high/ pulled highACKI (pu)1RDWRSDRASSDCASSDWEO/T (pu)1O/T (pu)1O/T (pu)1O/T (pu)1O/T (pu)1Pulled high/ driven highPulled high/ driven highPulled high/ driven highPulled high/ driven highPulled high/ driven highExternal Port Read Enable. RD is asserted whenever the processors read a word from external memory. External Port Write Enable. WR is asserted when the processors write a word to external memory. SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.Rev. A|Page 12 of 56|August 2006
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Table 5.Pin List
State During/ After Reset (ID = 00x)Pulled high/ driven highPulled high/ driven lowHigh-Z/drivingNameSDCKESDA10SDCLK0SDCLK1TypeO/T (pu)1O/T (pu)1O/TO/TDescriptionSDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal. For details, see the data sheet supplied with the SDRAM device.SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.SDRAM Clock Output 0. SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices, handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.MS0–1O/T (pu)1Pulled high/ driven highMemory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-sponding banks of external memory. The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the MS3-0 lines are inactive; they are active, however, when a condi-tional memory access instruction is executed, whether or not the condition is true. The MS1 pin can be used in EPORT/FLASH boot mode. See the hardware reference for more information.FLAG0/Interrupt Request 0.FLAG1/Interrupt Request 1.FLAG2/Interrupt Request 2/Memory Select 2.FLAG[0]/IRQ0FLAG[1]/IRQ1FLAG[2]/IRQ2/MS2FLAG[3]/TIMEXP/MS3TDITDOTMSTCKTRSTEMUCLK_CFG1–0I/OI/OI/O with pro-grammable pu (for MS mode)I/O with pro-grammable pu (for MS mode)I (pu)O/TI (pu)II (pu)O/T (pu)IHigh-Z/high-ZHigh-Z/high-ZHigh-Z/high-ZHigh-Z/high-ZFLAG3/Timer Expired/Memory Select 3.Test Data Input (JTAG). Provides serial data for the boundary scan logic. Test Data Output (JTAG). Serial scan output of the boundary scan path.Test Mode Select (JTAG). Used to control the test state machine. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up, or held low for proper operation of the processorTest Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board connectors only. Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table8 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset.Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. See Table7 for a description of the boot modes.BOOT_CFG1–0IRev. A|Page 13 of 56|August 2006
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Table 5.Pin List
State During/ After Reset (ID = 00x)NameRESETTypeIDescriptionProcessor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up.Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the processors to use either its internal clock generator or an external clock source. Con-necting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use an external clock such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency.XTALCLKINOIRESETOUT/CLKOUTO/TDriven low/driven highReset Out/Local Clock Out. Reset out provide a 4096 cycle delay that allows the PLL to lock. This pin can also be configured as a CLKOUT signal to clock synchronous periph-erals and memory. The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out.External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus master-ship. A processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a system with less than four processors, the unused BRx pins should be tied high; the processor’s own BRx line must not be tied high or low because it is an output.Processor ID. Determines which bus request (BR4–1) is used by the ADSP-21368 pro-cessor. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or 001 in single-processor systems. These lines are a system configuration selection that should be hardwired or only changed at reset. ID = 101,110, and 111 are reserved.Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for the ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every processor in the system.BR4–1I/O (pu)1Pulled high/pulled highID2–0I (pd)RPBAI (pu)112The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID2–0 = 00xPull-up can be enabled/disabled, value of pull-up cannot be programmed.
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DATA MODES
The upper 32 data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the exter-nal memory interface data (input/output), the PDAP (input only), the FLAGS (input/output), and the PWM channels (out-put). Table6 provides the pin settings.Table 6.Function of Data Pins
DATA PIN MODE000001010011100101110111
1DATA31–16
EPDATA32–0
FLAGS/PWM15–01FLAGS/PWM15–01FLAGS/PWM15–01PDAP (DATA + CTRL)PDAP (DATA + CTRL)
DATA15–8
EPDATA15–0
FLAGS15–8
FLAGS15–0
DATA7–0
EPDATA7–0EPDATA7–0FLAGS7–0
Reserved
Three-state all pins
These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals FLAGS/PWM_SEL. For more information, see the ADSP-21368 SHARC Processor Hardware Reference.
BOOT MODES
Table 7.Boot Mode Selection
BOOT_CFG1–0000110
Booting ModeSPI Slave BootSPI Master BootEPROM/FLASH Boot
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see Timing Specifications and Figure4 onPage19.
Table 8.Core Instruction Rate/CLKIN Ratio Selection
CLK_CFG1–0000110
Core to CLKIN Ratio6:132:116:1
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SPECIFICATIONSOPERATING CONDITIONS
333 MHz
Parameter1VDDINTAVDDVDDEXTVIH2 VIL2 VIH_CLKIN3 VIL_CLKIN3Description
Internal (Core) Supply VoltageAnalog (PLL) Supply VoltageExternal (I/O) Supply Voltage
High Level Input Voltage @ VDDEXT = maxLow Level Input Voltage @ VDDEXT = minHigh Level Input Voltage @ VDDEXT = maxLow Level Input Voltage @ VDDEXT = min
Min1.2351.2353.132.0–0.51.74–0.5
Max1.3651.3653.47VDDEXT + 0.5+0.8VDDEXT + 0.5+1.19
266 MHzMin1.141.143.132.0–0.51.74–0.50
0–40
+110+125
Max1.261.263.47VDDEXT + 0.5+0.8VDDEXT + 0.5+1.19+120
UnitVVVVVVV°C°C°C
Temperature TJ Junction 208-Lead MQFP @ TAMBIENT 0°C to +70°C 256-Ball SBGA @ TAMBIENT 0°C to +70°C 256-Ball SBGA @ TAMBIENT –40°C to +85°C
12Specifications subject to change without notice.
Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.3Applies to input pin CLKIN.
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ELECTRICAL CHARACTERISTICS
Parameter1VOH2VOL2IIH4, 5IIL4, 6, 7IIHPD6IILPU5IOZH 8, 9IOZL8, 10IOZLPU9IDD-INTYP11AIDD12CIN13, 1412Description
High Level Output Voltage Low Level Output VoltageHigh Level Input CurrentLow Level Input Current
High Level Input Current Pull-downLow Level Input Current Pull-upThree-State Leakage CurrentThree-State Leakage CurrentThree-State Leakage Current Pull-upSupply Current (Internal)Supply Current (Analog)Input Capacitance
Test Conditions
@ VDDEXT = min, IOH = –1.0 mA3@ VDDEXT = min, IOL = 1.0 mA3@ VDDEXT = max, VIN = VDDEXT max@ VDDEXT = max, VIN = 0 V@ VDDEXT = max, VIN = 0 V@ VDDEXT = max, VIN = 0 V@ VDDEXT = max, VIN = VDDEXT max@ VDDEXT = max, VIN = 0 V@ VDDEXT = max, VIN = 0 VtCCLK = 3.75 ns, VDDINT = 1.2 V, 25°CtCCLK = 3.00 ns, VDDINT = 1.3 V, 25°CAVDD = max
fIN = 1 MHz, TCASE = 25°C, VIN = 1.3 V
Min2.4
TypMaxUnitV
0.410102502001010200
700900
104.7
VμAμAμAμAμAμAμAmAmAmApF
Specifications subject to change without notice.
Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO, CLKOUT.3See Output Drive Currents on Page47 for typical drive current capabilities.4Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.5Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.6Applies to input pins with internal pull-downs: IDx.7Applies to input pins with internal pull-ups disabled: ACK, RPBA.8Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.9Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.10Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA1011See Engineer-to-Engineer Note 299 for further information. 12Characterized, but not tested.13Applies to all signal pins.14Guaranteed, but not tested.
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ADSP-21367/ADSP-21368/ADSP-21369
PACKAGE INFORMATION
The information presented in Figure3 provides details about the package branding for the ADSP-21367/ADSP-21368/
ADSP-21369 processors. For a complete listing of product avail-ability, see Ordering Guide on Page56.
MAXIMUM POWER DISSIPATION
See Engineer-to-Engineer Note (EE-299) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page48.
ABSOLUTE MAXIMUM RATINGS
aADSP-2136xtppZ-ccvvvvvv.xn.nyywwcountry_of_originSFigure 3.Typical Package Brand
Stresses greater than those listed in Table10 may cause perma-nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-tions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 10.Absolute Maximum Ratings
ParameterRating
Internal (Core) Supply Voltage (VDDINT)–0.3Vto+1.5VAnalog (PLL) Supply Voltage (AVDD)–0.3Vto+1.5V
VExternal (I/O) Supply Voltage (VDDEXT)–0.3V to+4.6
Input Voltage–0.5 V to +3.8 V Output Voltage Swing –0.5 V to VDDEXT + 0.5 VLoad Capacitance200 pFStorage Temperature Range–65°C to +150°CJunction Temperature Under Bias125°C
Table 9.Package Brand Information
Brand KeyField Description
t Temperature Range
pp Package TypeZ Lead Free Option (optional)ccSee Ordering Guide
vvvvvv.x Assembly Lot Coden.nSilicon RevisionyywwDate Code
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe ADSP-21367/ADSP-21368/ADSP-21369 feature proprietary ESD protection circuitry, permanentdamage may occur on devices subjected to high energy electrostatic discharges. Therefore, properESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADSP-21367/ADSP-21368/ADSP-21369
TIMING SPECIFICATIONS
The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the proces-sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins (see Table8 on Page15). To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider con-trol of each port (DIVx for the serial ports).
The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the sys-tem clock (CLKIN) signal and the processor’s internal clock.Figure4 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference.
Note the definitions of various clock periods shown in Table12 which are a function of CLKIN and the appropriate ratio con-trol shown in Table11.
Table 11.ADSP-21367/ADSP-21368/ADSP-21369 CLKOUT and CCLK Clock Generation Operation
Timing
RequirementsDescriptionCalculationCLKN nput Clock1/tCK CCLKCore Clock1/tCCLKTable 12.Clock Periods
Timing
RequirementstCKtCCLKtPCLKtSCLKtSDCLKtSPICLK1Description1CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × tCCLKSerial Port Clock Period = (tPCLK) × SRSDRAM Clock Period = (tCCLK) × SDRSPI Clock Period = (tPCLK) × SPIR
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV bits in DIVx register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register setting)
SPICLK = SPI Clock
SDR = SDRAM-to-Core Clock Ratio (values determined by bits 20–18 of the PMCTL register)
PLLICLKCLKINXTALXTALOSCINDIV÷1,2PLLMDIVENI÷2,4,8,16CCLK(CORECLOCK)I÷2PCLK(PERIPHERALCLOCK)CLK_CFG[1:0](6:1,16:1,32:1)÷2,2.5,3,3.5,4SDCLK(SDRAMCLOCK)CLKOUTORRSTOUTRESETDELAYFigure 4.Core Clock and System Clock Relationship to CLKIN
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Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure39 on Page47 under Test Conditions for voltage refer-ence levels.
Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching char-acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-cuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
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Power-Up Sequencing
The timing requirements for processor startup are given in Table13.
Table 13.Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing RequirementstRSTVDDtIVDDEVDDtCLKVDD1tCLKRSTtPLLRSTMin
RESET Low Before VDDINT/VDDEXT OnVDDINT On Before VDDEXTCLKIN Valid After VDDINT/VDDEXT ValidCLKIN Valid Before RESET DeassertedPLL Control Setup Before RESET Deasserted0–50010220
Max
Unitnsmsmsμsμs
+200+200
Switching Characteristic
Core Reset Deasserted After RESET DeassertedtCORERST14096tCK + 2 tCCLK 3, 4Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.2Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.3Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate default states at all I/O pins.4The 4096 cycle count depends on tsrst specification in Table15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum.
RESETtRSTVDDVDDINTtIVDDEVDDVDDEXTtCLKVDDCLKINtCLKRSTCLK_CFG1-0tPLLRSTRSTOUTtCORERSTFigure 5.Power-Up Sequencing
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Clock Input
Table 14.Clock Input
Parameter
Timing RequirementstCKCLKIN PeriodtCKLCLKIN Width LowtCKHCLKIN Width HightCKRFCLKIN Rise/Fall (0.4 V to 2.0 V)
3tCCLKCCLK Period4, 5CLKIN Jitter TolerancetCKJ12Min1818181 3.01–250
333 MHz
Max
1002452452310+250
Unitnsnsnsnsnsps
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.Applies only for CLK_CFG1–0 = 10 and default values for PLL control bits in PMCTL.3Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.4Actual input jitter should be combined with ac specifications for accurate timing analysis.5Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
tCKCLKINtCKHtCKLFigure 6.Clock Input
Clock Signals
The processors can use an external clock or a crystal. See the CLKIN pin description in Table5. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure7 shows the component connections used for a crystal operating in funda-mental mode. Note that the clock rate is achieved using a 20.81 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 333 MHz). To achieve the full core clock rate, programs need to configure the multi-plier bits in the PMCTL register.
ADSP-2136xCLKINR11M⍀(TYPICAL)XTALR247⍀(TYPICAL)C122pFY124.576MHzC222pFR2SHOULDBECHOSENTOLIMITCRYSTALDRIVEPOWER.REFERTOCRYSTALMANUFACTURER’SSPECIFICATIONSFigure 7.333 MHz Operation (Fundamental Mode Crystal)
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ResetTable 15.Reset
Parameter
Timing RequirementstWRST1RESET Pulse Width LowtSRSTRESET Setup Before CLKIN Low1Min4tCK8
MaxUnitnsns
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than100μs while RESET is low, assuming stable VDD and CLKIN (not including startup time of external clock oscillator).
CLKINtWRSTRESETtSRSTFigure 8.Reset
Interrupts
The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts.Table 16.Interrupts
Parameter
Timing RequirementtIPW IRQx Pulse WidthMin2 × tPCLK +2
Max
Unitns
DAI_P20-1DPI_14-1FLAG2-0(IRQ2-0)tIPWFigure 9.Interrupts
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Core Timer
The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 17.Core Timer
Parameter
Switching CharacteristictWCTIMCTIMER Pulse Width
in4 × tPCLK – 1
ax Unitns
FLAG3(CTIMER)tWCTIMMM
Figure 10.Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins.Table 18.Timer PWM_OUT Timing
Parameter
Switching CharacteristictPWMOTimer Pulse Width Output
in
ax Unitns
2 × tPCLK – 22 × (231 – 1) × tPCLKMM
DPI_P14-1(TIMER2-0)tPWMOFigure 11.Timer PWM_OUT Timing
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Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specification provided below are valid at the DPI_P14–1 pins.Table 19.Timer Width Capture Timing
Parameter
Switching CharacteristictPWITimer Pulse Width
in2 × tPCLK
ax Unit2 × (231 – 1) × tPCLKns
tPWIDPI_P14-1(TIMER2-0)Figure 12.Timer Width Capture Timing
Pin to Pin Direct Routing (DAI and DPI)
For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O).
Table 20.DAI Pin to Pin Routing
ParameterMin
MMTiming RequirementtDPIODelay DAI Pin Input Valid to DAI Output Valid1.5
Max10
Unitns
DAI_PnDPI_PnDAI_pmDPI_PmtDPIOFigure 13.DAI Pin to Pin Direct Routing
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Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 21.Precision Clock Generator (Direct Pin Routing)
ParameterMinMaxUnitTiming RequirementstPCGIPInput Clock Period24nstSTRIGPCG Trigger Setup Before Falling 4.5ns
Edge of PCG Input Clock
tHTRIGPCG Trigger Hold After Falling 3ns
Edge of PCG Input Clock
Switching CharacteristicstDPCGIOPCG Output Clock and Frame Sync Active Edge
Delay After PCG Input Clock2.510ns
tDTRIGCLKPCG Output Clock Delay After PCG Trigger2.5 + ((2.5 + D) × tPCGIP)10 + ((2.5 + D) × tPCGIP)nstDTRIGFSPCG Frame Sync Delay After PCG Trigger2.5 + ((2.5 + D – PH) × tPCGIP)10 + ((2.5 + D – PH) × tPCGIP)nstPCGOW1Output Clock Period2 × tPCGIP – 1ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor, “Precision Clock Generators” chapter.
1inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing param-eters and switching characteristics apply to external DAI pins (DAI_P01 – DAI_P20).
In normal mode.
tSTRIGDAI_PnDPI_PnPCG_TRIGx_ItHTRIGtPCGIPDAI_PmDPI_PmPCG_EXTx_I(CLKIN)tDPCGIODAI_PyDPI_PyPCG_CLKx_OtDTRIGCLKtDPCGIOtPCGOWDAI_PzDPI_PzPCG_FSx_OtDTRIGFSFigure 14.Precision Clock Generator (Direct Pin Routing)
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Flags
The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). See Table5 on Page12 for more information on flag use.Table 22.Flags
Parameter
Timing Requirement
FLAG3–0 IN Pulse WidthtFIPWSwitching CharacteristictFOPWFLAG3–0 OUT Pulse Width
in2 × tPCLK + 32 × tPCLK – 1.5
ax Unitnsns
DPI_P14-1(FLAG3-0IN)(DATA31-0)tFIPWDPI_P14-1(FLAG3-0OUT)(DATA31-0)tFOPWFigure 15.Flags
MM
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SDRAM Interface Timing (133 MHz SDCLK)
The 133 MHz access speed is for a single processor. When mul-tiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz.Table 23.SDRAM Interface Timing1Parameter
Timing Requirements
DATA Setup Before SDCLKtSSDATtHSDATDATA Hold After SDCLKSwitching CharacteristicstSDCLKSDCLK PeriodtSDCLKHSDCLK Width HightSDCLKLSDCLK Width Low
Command, ADDR, Data Delay After SDCLK2tDCADtHCADCommand, ADDR, Data Hold After SDCLK2tDSDATData Disable After SDCLKtENSDATData Enable After SDCLK
12Min0.58
1.237.53.653.65
MaxUnitnsnsnsnsnsnsnsnsns
4.8
1.5
5.3
1.6
For FCCLK = 333 MHz (SDCLK ratio = 1:2.5).
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.tSDCLKSDCLKtSDCLKHtSSDATtHSDATDATA(IN)tSDCLKLtDCADtENSDATDATA(OUT)tDSDATtHCADtDCADCMNDADDR(OUT)tHCADFigure 16.SDRAM Interface Timing
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SDRAM Interface Enable/Disable Timing (133 MHz SDCLK)Table 24.SDRAM Interface Enable/Disable Timing1Parameter
Switching CharacteristicstDSDCCommand Disable After CLKIN RisetENSDCCommand Enable After CLKIN RisetDSDCCSDCLK Disable After CLKIN RisetENSDCCSDCLK Enable After CLKIN RisetDSDCAAddress Disable After CLKIN RisetENSDCAAddress Enable After CLKIN Rise
1MinMax2 × tPCLK + 1
Unitns
nsnsnsnsns
4.0
8.5
3.82 × tPCLK – 4
9.24 × tPCLKFor FCCLK = 333 MHz (SDCLK ratio = 1:2.5).
CLKINtDSDCtDSDCCtDSDCACOMMANDSDCLKADDRCOMMANDSDCLKADDRtENSDCtENSDCCtENSDCAFigure 17.SDRAM Interface Enable/Disable Timing
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Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-ries. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 25.Memory Read—Bus Master
Parameter
Timing RequirementstDADAddress, Selects Delay to Data Valid1, 2tDRLDRD Low to Data Valid1tSDSData Setup to RD HightHDRHData Hold from RD High3, 4tDAAKACK Delay from Address, Selects2, 5tDSAKACK Delay from RD Low4Min
Max
W+tSDCLK –5.12
W– 2.9
2.20
tSDCLK–9.5+ WW – 7.0
Unitns ns ns nsns ns ns nsnsns
Switching CharacteristicstDRHAAddress Selects Hold After RD HighRH + 0.38
2tDARLAddress Selects to RD LowtSDCLK –3.3tRWRD Pulse WidthW – 1.2tRWRRD High to WR, RD LowHI +tSDCLK – 0.8W = (number of wait states specified in AMICTLx register) × tSDCLK.
HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × tSDCLK IC = (number of idle cycles specified in AMICTLx register) × tSDCLK.H = (number of hold cycles specified in AMICTLx register) × tSDCLK.
12Data delay/setup: system must meet tDAD, tDRLD, or tSDS.The falling edge of MSx is referenced.3Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.4Data hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page47 for the calculation of hold times given capacitive and dc loads.5ACK Delay/Setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
ADDRESSMSxRDtDARLtRWtDRHAtDRLDtDADDATAtSDStHDRHtDSAKtDAAKACKtRWRWRFigure 18.Memory Read—Bus Master
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Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-ries. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 26.Memory Write—Bus Master
Parameter
Timing RequirementstDAAKACK Delay from Address, Selects1, 2tDSAKACK Delay from WR Low 1, 3Switching CharacteristicstDAWHAddress, Selects to WR Deasserted2Address, Selects to WR Low2tDAWLtWWWR Pulse WidthtDDWHData Setup Before WR HightDWHAAddress Hold After WR DeassertedtDWHDData Hold After WR DeassertedtWWRWR High to WR, RD LowData Disable Before RD LowtDDWRtWDEWR Low to Data EnabledW = (number of wait states specified in AMICTLx register) × tSDCLK.H = (number of hold cycles specified in AMICTLx register) x tSDCLK.
12MinMaxtSDCLK – 9.7 + WW – 4.9
Unitns ns ns ns ns ns ns ns ns nsns
tSDCLK–3.1+ WtSDCLK–2.7W – 1.3
tSDCLK–3.0+ WH + 0.15H + 0.02
tSDCLK–1.5+ H2tSDCLK– 4.11tSDCLK– 3.5
ACK Delay/Setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.The falling edge of MSx is referenced.3Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.ADDRESSMSxtDAWHtDAWLWRtDWHAtWWtWDEtDDWHDATAtWWRtDDWRtDSAKtDAAKACKtDWHDRDFigure 19.Memory Write—Bus Master
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Asynchronous Memory Interface (AMI) Enable/DisableUse these specifications for passing bus mastership between ADSP-21368 processors (BRx).Table 27.AMI Enable/Disable
Parameter
Switching CharacteristicstENAMIACAddress/Control Enable After Clock RisetENAMIDData Enable After Clock RisetDISAMIACAddress/Control Disable After Clock RisetDISAMIDData Disable After Clock Rise
in4
tSCLK + 4
8.70
ax Unitns ns ns ns
CLKINtDISAMIACtDISAMIDADDR,WR,RD,MS1-0,DATAtENAMIACtENAMIDADDR,WR,RD,MS1-0,DATAFigure 20.AMI Enable/Disable
MM
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Shared Memory Bus Request
Use these specifications for passing bus mastership between ADSP-21368 processors (BRx).Table 28.Multiprocessor Bus Request
Parameter
Timing RequirementstSBRIBRx, Setup Before CLKIN HightHBRIBRx, Hold After CLKIN HighSwitching CharacteristicstDBROBRx Delay After CLKIN HighBRx Hold After CLKIN HightHBROMin9
0.5
9
1.0
Max
Unitns ns ns ns
CLKINtDBROtHBROBRX(OUT)tSBRIBRX(IN)tHBRIFigure 21.Shared Memory Bus Request
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Serial Ports
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.Table 29.Serial Ports—External Clock
Parameter
Timing RequirementstSFSE1FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tHFSE1FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tSDRE1Receive Data Setup Before Receive SCLKtHDRE1Receive Data Hold After SCLKtSCLKWSCLK WidthtSCLKSCLK PeriodSwitching CharacteristicstDFSE2FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)FS Hold After SCLK tHOFSE2(Internally Generated FS in Either Transmit or Receive Mode)
tDDTE2Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLKtHDTE212Serial port signals (SCLK, FS, data channel A, data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.
inax Unit2.5
M2.52.52.51020
M
ns ns ns ns ns ns
9.5
2
9.6
2
M
M
ns ns ns ns
Referenced to sample edge.Referenced to drive edge.
Table 30.Serial Ports—Internal Clock
Parameter
Timing RequirementstSFSI1FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1tHFSIFS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)Receive Data Setup Before SCLKtSDRI1tHDRI1Receive Data Hold After SCLKSwitching CharacteristicstDFSI2FS Delay After SCLK (Internally Generated FS in Transmit Mode)
2tHOFSIFS Hold After SCLK (Internally Generated FS in Transmit Mode)
2tDFSIRFS Delay After SCLK (Internally Generated FS in Receive Mode)
2FS Hold After SCLK (Internally Generated FS in Receive Mode)tHOFSIR2tDDTITransmit Data Delay After SCLK2tHDTITransmit Data Hold After SCLK
3tSCLKIWTransmit or Receive SCLK Width
12inax Unit72.5
72.5
4
–1.0
9
–1.0
3
–1.0
2 × tPCLK – 1.5
2 × tPCLKns ns ns ns ns nsnsnsns ns ns
Referenced to the sample edge.Referenced to drive edge.3Minimum SPORT divisor register value.
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Table 31.Serial Ports—Enable and Three-State
Parameter
Switching CharacteristicstDDTEN1Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLKtDDTTE1tDDTIN1Data Enable from Internal Transmit SCLK
1in2
ax Unitns
ns ns
10
–1
Referenced to drive edge.
Table 32.Serial Ports—External Late Frame Sync
Parameter
Switching CharacteristicstDDTLFSE1Data Delay from Late External Transmit FS or External Receive
FS with MCE = 1, MFD = 0
1tDDTENFSData Enable for MCE = 1, MFD = 0
1inax Unit7.75
0.5ns
ns
The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
EXTERNALRECEIVEFSWITHMCE=1,MFD=0DAI_P20-1(SCLK)DRIVESAMPLEDRIVEtSFSE/IDAI_P20-1(FS)tHFSE/IMtDDTENFStDDTE/ItHDTE/I1STBITtDDTLFSEMDAI_P20-1(DATACHANNELA/B)2NDBITMLATEEXTERNALTRANSMITFSDRIVESAMPLEDRIVEMDAI_P20-1(SCLK)tSFSE/IDAI_P20-1(FS)tHFSE/ItDDTENFSDAI_P20-1(DATACHANNELA/B)tDDTE/ItHDTE/I1STBIT2NDBITtDDTLFSENOTE:SERIALPORTSIGNALS(SCLK,FS,DATACHANNELA/B)AREROUTEDTOTHEDAI_P20-1PINSUSINGTHESRU.THETIMINGSPECIFICATIONSPROVIDEDHEREAREVALIDATTHEDAI_P20-1PINS.Figure 22.External Late Frame Sync11This figure reflects changes made to support left-justified sample pair mode.
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DATARECEIVE—INTERNALCLOCKDRIVEEDGESAMPLEEDGEDATARECEIVE—EXTERNALCLOCKDRIVEEDGESAMPLEEDGEtSCLKIWDAI_P20-1(SCLK)DAI_P20-1(SCLK)tSCLKWtDFSIRtHOFSIRDAI_P20-1(FS)tSFSItHFSIDAI_P20-1(FS)tDFSEtHOFSEtSFSEtHFSEtSDRIDAI_P20-1(DATACHANNELA/B)tHDRIDAI_P20-1(DATACHANNELA/B)tSDREtHDRENOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFSCLK(EXTERNAL),SCLK(INTERNAL)CANBEUSEDASTHEACTIVESAMPLINGEDGE.DATATRANSMIT—INTERNALCLOCKDRIVEEDGESAMPLEEDGEDATATRANSMIT—EXTERNALCLOCKDRIVEEDGESAMPLEEDGEtSCLKIWDAI_P20-1(SCLK)DAI_P20-1(SCLK)tSCLKWtDFSItHOFSIDAI_P20-1(FS)tSFSItHFSIDAI_P20-1(FS)tDFSEtHOFSEtSFSEtHFSEtHDTIDAI_P20-1(DATACHANNELA/B)tDDTIDAI_P20-1(DATACHANNELA/B)tHDTEtDDTENOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFSCLK(EXTERNAL),SCLK(INTERNAL)CANBEUSEDASTHEACTIVESAMPLINGEDGE.DRIVEEDGEDAI_P20-1SCLK(EXT)SCLKDRIVEEDGEtDDTENtDDTTEDAI_P20-1(DATACHANNELA/B)DRIVEEDGEDAI_P20-1SCLK(INT)tDDTINDAI_P20-1(DATACHANNELA/B)Figure 23.Serial Ports
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ADSP-21367/ADSP-21368/ADSP-21369
Input Data Port
The timing requirements for the IDP are given in Table33. IDP signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.Table 33.IDP
Parameter
Timing RequirementstSISFS1FS Setup Before SCLK Rising EdgetSIHFS1FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising EdgetSISD1tSIHD1SDATA Hold After SCLK Rising EdgetIDPCLKWClock WidthtIDPCLKClock Period
1in3.8
2.52.52.5924
ax Unitns ns ns ns ns ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLEEDGEtIDPCLKDAI_P20-1(SCLK)tIDPCLKWtSISFSDAI_P20-1(FS)tSIHFStSISDDAI_P20-1(SDATA)MtSIHDMFigure 24.IDP Master Timing
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ADSP-21367/ADSP-21368/ADSP-21369
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table34. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-21368 SHARC Processor Hardware Table 34.Parallel Data Acquisition Port (PDAP)
Parameter
Timing RequirementstSPCLKEN1PDAP_CLKEN Setup Before PDAP_CLK Sample EdgetHPCLKEN1PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample EdgetPDSD1tPDHD1PDAP_DAT Hold After SCLK PDAP_CLK Sample EdgetPDCLKWClock WidthtPDCLKClock PeriodSwitching CharacteristicstPDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse WidthtPDSTRB1Reference. Note that the most significant 16 bits of external
PDAP data can be provided through the DATA31–16 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DATA31–16 pins.
Min2.52.53.852.57.0242 × tPCLK + 32 × tPCLK – 1
MaxUnitnsns ns ns ns ns ns ns
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SAMPLEEDGEtPDCLKtPDCLKWDAI_P20-1(PDAP_CLK)tSPCLKENDAI_P20-1(PDAP_CLKEN)tHPCLKENtPDSDDATAtPDHDDAI_P20-1(PDAP_STROBE)tPDSTRBtPDHLDDFigure 25.PDAP Timing
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ADSP-21367/ADSP-21368/ADSP-21369
Pulse-Width Modulation GeneratorsTable 35.PWM Timing
Parameter
Switching CharacteristicstPWMWPWM Output Pulse WidthtPWMPPWM Output Period
intPCLK – 2
2 × tPCLK – 1.5
ax Unit(216 – 2) × tPCLK – 2(216 – 1) × tPCLK – 1.5
nsns
tPWMWPWMOUTPUTStPWMPFigure 26.PWM Timing
MM
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing spec-ifications provided in Table36 are valid at the DAI_P20–1 pins.Table 36.SRC, Serial Input Port
Parameter
Timing RequirementstSRCSFS1FS Setup Before SCLK Rising EdgetSRCHFS1FS Hold After SCLK Rising EdgetSRCSD1SDATA Setup Before SCLK Rising Edge
MtSRCHD1SDATA Hold After SCLK Rising Edge
tSRCCLKWClock Width
Clock PeriodtSRCCLK1in
4
5.54
M5.5
924
ax Unitns ns ns ns ns ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLEEDGEtSRCCLKDAI_P20-1(SCLK)tSRCCLKWtSRCSFSDAI_P20-1(FS)tSRCHFStSRCSDDAI_P20-1(SDATA)tSRCHDFigure 27.SRC Serial Input Port Timing
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ADSP-21367/ADSP-21368/ADSP-21369
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 37.SRC, Serial Output Port
Parameter
Timing Requirements
FS Setup Before SCLK Rising EdgetSRCSFS11tSRCHFSFS Hold After SCLK Rising EdgetSRCCLKWClock WidthtSRCCLKClock PeriodSwitching CharacteristicstSRCTDD1Transmit Data Delay After SCLK Falling Edge
1Transmit Data Hold After SCLK Falling EdgetSRCTDH1and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the drive edge.
in45.5924
ax Unitns ns ns ns
8.9
ns ns
1
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLEEDGEtSRCCLKDAI_P20-1(SCLK)tSRCCLKWtSRCSFSDAI_P20-1(FS)tSRCHFSMtSRCTDDMDAI_P20-1(SDATA)tSRCTDHFigure 28.SRC Serial Output Port Timing
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ADSP-21367/ADSP-21368/ADSP-21369
SPDIF Transmitter
Serial data input to the SPDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter.
SPDIF Transmitter—Serial Input Waveforms
Figure29 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising edge of SCLK. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data is right-justified to the next LRCLK transition.
DAI_P20-1LRCLKDAI_P20-1SCLKDAI_P20-1SDATALSBLEFTCHANNELRIGHTCHANNELMSBMSB-1MSB-2LSB+2LSB+1LSBMSBMSB-1MSB-2LSB+2LSB+1LSBFigure 29.Right-Justified Mode
Figure30 shows the default I2S-justified mode. LRCLK is LO for the left channel and HI for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition but with a single SCLK period delay.
DAI_P20-1LRCLKDAI_P20-1SCLKDAI_P20-1SDATAMSBMSB-1MSB-2RIGHTCHANNELLEFTCHANNELLSB+2LSB+1LSBMSBMSB-1MSB-2LSB+2LSB+1LSBMSBFigure 30.I2S-Justified Mode
Figure31 shows the left-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition with no MSB delay.
DAI_P20-1LRCLKDAI_P20-1SCLKDAI_P20-1SDATAMSBMSB-1MSB-2LEFTCHANNELRIGHTCHANNELLSB+2LSB+1LSBMSBMSB-1MSB-2LSB+2LSB+1LSBMSBMSB+1Figure 31.Left-Justified Mode
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ADSP-21367/ADSP-21368/ADSP-21369
SPDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table38. Input signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica-tions provided below are valid at the DAI_P20–1 pins.Table 38.SPDIF Transmitter Input Data Timing
Parameter
Timing RequirementstSISFS1FS Setup Before SCLK Rising Edge
1tSIHFSFS Hold After SCLK Rising Edge1tSISDSData Setup Before SCLK Rising EdgetSIHD1SData Hold After SCLK Rising Edge
Clock WidthtSISCLKWtSISCLKClock PeriodtSITXCLKWTransmit Clock WidthtSITXCLKTransmit Clock Period
1in3
3333680920
ax Unitns ns ns ns ns ns ns ns
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLEEDGEDAI_P20-1(TXCLK)tSITXCLKWtSITXCLKDAI_P20-1(SCLK)tSISCLKWMMtSISFSDAI_P20-1(FS)tSIHFStSISDDAI_P20-1(SDATA)tSIHDFigure 32.SPDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching CharacteristicsThe SPDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock.
Table 39.Oversampling Clock (TxCLK) Switching Characteristics
Parameter
TxCLK Frequency for TxCLK = 768 × FSTxCLK Frequency for TxCLK = 512 × FSTxCLK Frequency for TxCLK = 384 × FSTxCLK Frequency for TxCLK = 256 × FSFrame Rate
Min
Max147.598.473.849.2192.0
UnitMHzMHzMHzMHzkHz
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SPDIF Receiver
The following section describes timing as it relates to the SPDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock.
Table 40.SPDIF Receiver Internal Digital PLL Mode Timing
Parameter
Switching Characteristics
LRCLK Delay After SCLKtDFSItHOFSILRCLK Hold After SCLKtDDTITransmit Data Delay After SCLKtHDTITransmit Data Hold After SCLKtSCLKIW1Transmit SCLK Width
1MinMax5
Unitns
nsnsnsns
–2
5
–240
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DRIVEEDGEtSCLKIWDAI_P20-1(SCLK)SAMPLEEDGEtDFSItHOFSIDAI_P20-1(FS)tHDTIDAI_P20-1(DATACHANNELA/B)tDDTIFigure 33.SPDIF Receiver Internal Digital PLL Mode Timing
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ADSP-21367/ADSP-21368/ADSP-21369
SPI Interface—Master
The processors contain two SPI ports. The primary has dedi-cated pins and the secondary is available through the DPI. The timing provided in Table41 and Table42 on Page45 applies to both.
Table 41.SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing RequirementstSSPIDMData Input Valid to SPICLK Edge (Data Input Setup Time)tHSPIDMSPICLK Last Sampling Edge to Data Input Not ValidSwitching CharacteristicstSPICLKMSerial Clock Cycle tSPICHMSerial Clock High Period tSPICLMSerial Clock Low Period tDDSPIDMSPICLK Edge to Data Out Valid (Data Out Delay Time)tHDSPIDMSPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK EdgetSDSCIMtHDSMLast SPICLK Edge to FLAG3–0IN HightSPITDMSequential Transfer Delay
in8.2
2
8 × TPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2
2.5
2
4 × tPCLK – 24 × tPCLK – 2 4 × tPCLK – 1
ax Unitnsnsnsnsnsnsnsnsnsns
FLAG3-0(OUTPUT)tSDSCIMSPICLK(CP=0)(OUTPUT)tSPICHMtSPICLMtSPICLKMtHDSMtSPITDMMMtSPICLMSPICLK(CP=1)(OUTPUT)tSPICHMtDDSPIDMMOSI(OUTPUT)CPHASE=1MISO(INPUT)MSBVALIDMSBtHDSPIDMLSBtSSPIDMtHSPIDMtSSPIDMLSBVALIDtHSPIDMtDDSPIDMMOSI(OUTPUT)CPHASE=0MISO(INPUT)MSBtHDSPIDMLSBtSSPIDMMSBVALIDtHSPIDMLSBVALIDFigure 34.SPI Master Timing
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ADSP-21367/ADSP-21368/ADSP-21369
SPI Interface—Slave
Table 42.SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing RequirementstSPICLKStSPICHStSPICLStSDSCOin4 × tPCLK – 22 × tPCLK – 22 × tPCLK – 22 × tPCLK2 × tPCLK2 × tPCLK22
2 × tPCLK002 × tPCLK5 × tPCLK6.86.89.5
ax Unitnsnsnsnsnsnsnsnsnsnsnsnsnsns
Serial Clock Cycle
Serial Clock High Period Serial Clock Low Period
SPIDS Assertion to First SPICLK EdgeCPHASE = 0CPHASE = 1
tHDSLast SPICLK Edge to SPIDS Not Asserted, CPHASE = 0tSSPIDSData Input Valid to SPICLK Edge (Data Input Setup Time)tHSPIDSSPICLK Last Sampling Edge to Data Input Not ValidtSDPPWSPIDS Deassertion Pulse Width (CPHASE = 0)Switching CharacteristicstDSOESPIDS Assertion to Data Out ActivetDSDHISPIDS Deassertion to Data High ImpedancetDDSPIDSSPICLK Edge to Data Out Valid (Data Out Delay Time)tHDSPIDSSPICLK Edge to Data Out Not Valid (Data Out Hold Time)tDSOVSPIDS Assertion to Data Out Valid (CPHASE = 0)SPIDS(INPUT)tSPICHSSPICLK(CP=0)(INPUT)tSPICLStSPICLKStHDSMtSDPMPWtSDSCOSPICLK(CP=1)(INPUT)tSPICLStSPICHStDSOEtDDSPIDStDSDHItDDSPIDSMSBLSBtHDSPIDSMISO(OUTPUT)CPHASE=1MOSI(INPUT)tSSPIDSMSBVALIDtHSPIDStSSPIDSLSBVALIDtDSOVtDSOEMISO(OUTPUT)CPHASE=0MOSI(INPUT)MSBVALIDMSBtDDSPIDStHDSPIDSLSBtDSDHItSSPIDSLSBVALIDtHSPIDSFigure 35.SPI Slave Timing
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ADSP-21367/ADSP-21368/ADSP-21369
JTAG Test Access Port and EmulationTable 43.JTAG Test Access Port and Emulation
Parameter
Timing RequirementstTCKTCK PeriodtSTAPTDI, TMS Setup Before TCK HightHTAPTDI, TMS Hold After TCK High1tSSYSSystem Inputs Setup Before TCK High
1tHSYSSystem Inputs Hold After TCK High tTRSTWTRST Pulse WidthSwitching CharacteristicstDTDOTDO Delay from TCK LowtDSYS2System Outputs Delay After TCK Low
12intCK567184tCKax Unitnsnsnsnsnsns
7
tCK ÷ 2 + 7
nsns
System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU.tTCKTCKtSTAPTMSTDItDTDOTDOtSSYSSYSTEMINPUTStDSYSSYSTEMOUTPUTStHSYStHTAPMMFigure 36.IEEE 1149.1 JTAG Test Access Port
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ADSP-21367/ADSP-21368/ADSP-21369
OUTPUT DRIVE CURRENTS
Figure37 shows typical I-V characteristics for the output driv-ers of the ADSP-21367/ADSP-21368/ADSP-21369. The curves represent the current drive capability of the output drivers as a function of output voltage.
INPUT1.5VOROUTPUT1.5VFigure 39.Voltage Reference Levels for AC Measurements
4030SOURCE(VDDEXT)CURRENT(mA)CAPACITIVE LOADING
VOH3.3V,25°C3.47V,-45°C3.11V,125°C20100-10Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure38). Figure42 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure40, Figure41, and Figure42 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance.
3.11V,125°C-203.3V,25°C-30-40VOL3.47V,-45°C00.512RISEANDFALLTIMES(ns)1.01.52.02.5SWEEP(VDDEXT)VOLTAGE(V)3.03.510y=0.0467x+1.63238RISEFALLFigure 37.Typical Drive at Junction temperature
6TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table15 on Page23 through Table43 on Page46. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure39.
Timing is measured on signals when they cross the 1.5V level as described in Figure39. All delays (in nanoseconds) are mea-sured between the point that the first signal reaches 1.5V and the point that the second signal reaches 1.5V.
4y=0.045x+1.52420050100150200250LOADCAPACITANCE(pF)Figure 40.Typical Output Rise/Fall Time (20% to 80%,
VDDEXT = Max)
12IOLRISE10RISEANDFALLTIMES(ns)y=0.049x+1.51058FALL50⍀1.5V+TOOUTPUTPIN6y=0.0482x+1.4604430pFIOH20Figure 38.Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
050100150200250LOADCAPACITANCE(pF)Figure 41.Typical Output Rise/Fall Time (20% to 80%,
VDDEXT = Min)
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ADSP-21367/ADSP-21368/ADSP-21369
108OUTPUTDELAYORHOLD(ns)Values of θJB are provided for package comparison and PCB design considerations. Note that the thermal characteristics val-ues provided in Table44 and Table45 are modeled values.
Y=0.0488x-1.59236420-2-4Table 44.Thermal Characteristics for 256-Ball SBGA
ParameterθJAθJMAθJMAθJCθJBΨJTΨJMTΨJMTConditionAirflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/s
Typical12.510.69.90.75.30.30.30.3
Unit°C/W°C/W°C/W°C/W°C/W°C/W°C/W°C/W
050100150200LOADCAPACITANCE(pF)Airflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/s
Figure 42.Typical Output Delay or Hold vs. Load Capacitance
(at Junction Temperature)
Table 45.Thermal Characteristics for 208-Lead MQFP
ParameterθJAθJMAθJMAθJCΨJTΨJMTΨJMTConditionAirflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/sAirflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/s
Typical25.022.521.69.60.70.80.9
Unit°C/W°C/W°C/W°C/W°C/W°C/W°C/W
THERMAL CHARACTERISTICS
The ADSP-21367/ADSP-21368/ADSP-21369 processors are rated for performance over the temperature range specified in Operating Conditions on Page16.
Table44 and Table45 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. Test board design complies with JEDEC standard JESD51-9 (SBGA) and
JESD51-7 (MQFP). The junction-to-case measurement com-plies with MIL-STD-883. All measurements use a 2S2P JEDEC test board.
To determine the junction temperature of the device while on the application PCB, use:
TJ=TTOP+(ΨJT×PD)
where:
TJ = junction temperature (°C)
TTOP = case temperature (°C) measured at the top center of the package
ΨJT = junction-to-top (of package) characterization parameter
is the typical value from Table44 and Table45.PD = power dissipation (see EE Note EE-299)
Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approxi-mation of TJ by the equation:
TJ=TA+(θJA×PD)
where:
TA = ambient temperature (°C)
Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. This is only applicable when a heat sink is used.
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ADSP-21367/ADSP-21368/ADSP-21369
256-BALL SBGA PINOUTTable 46.256-Ball SBGA Pin Assignment (Numerically by Ball Number)
Ball No.A01A02A03A04A05A06A07A08A09A10A11A12A13A14A15A16A17A18A19A20E01E02E03E04E17E18E19E20J01J02J03J04
SignalNCTDITMS
CLK_CFG0CLK_CFG1EMUDAI4DAI1DPI14DPI12DPI10DPI9DPI7DPI6DPI3DPI2CLKOUTDATA31NCNCDAI11DAI8VDDINTVDDINTGNDGNDDATA25DATA23DAI19DAI18GNDGND
Ball No.B01B02B03B04B05B06B07B08B09B10B11B12B13B14B15B16B17B18B19B20F01F02F03F04F17F18F19F20K01K02K03K04
SignalDAI5SDCLK1TRSTTCK
BOOT_CFG_0BOOT_CFG_1TDODAI3DAI2DPI13DPI11DPI8DPI5DPI4DPI1RESETDATA30DATA29DATA28NCDAI14DAI12GNDGNDVDDEXTGND
GND/ID21DATA21FLAG0DAI20GNDVDDEXTBall No.C01C02C03C04C05C06C07C08C09C10C11C12C13C14C15C16C17C18C19C20G01G02G03G04G17G18G19G20L01L02L03L04
SignalDAI9DAI7GNDVDDEXTGNDGNDVDDINTGNDGNDVDDINTGNDGNDVDDINTGNDGNDVDDINTVDDINTVDDINTDATA27NC/RPBA1DAI15DAI13GNDVDDEXTVDDINTVDDINTDATA22DATA20FLAG2FLAG1VDDINTVDDINTBall No.D01D02D03D04D05D06D07D08D09D10D11D12D13D14D15D16D17D18D19D20H01H02H03H04H17H18H19H20M01M02M03M04
SignalDAI10DAI6GNDVDDEXTGNDVDDEXTVDDINTGNDVDDEXTVDDINTGNDVDDEXTVDDINTGNDVDDEXTGNDVDDEXTGNDDATA26DATA24DAI17DAI16VDDINTVDDINTVDDEXTGNDDATA19DATA18ACKFLAG3GNDGND
Rev. A|Page 49 of 56|August 2006
ADSP-21367/ADSP-21368/ADSP-21369
Table 46.256-Ball SBGA Pin Assignment (Numerically by Ball Number) (Continued)
Ball No.J17J18J19J20N01N02N03N04N17N18N19N20U01U02U03U04U05U06U07U08U09U10U11U12U13U14U15U16U17U18U19U20
1SignalGNDGND
GND/ID11DATA17RDSDCLK0GNDVDDEXTGNDGNDDATA11DATA10MS0MS1VDDINTGNDVDDEXTGNDVDDEXTVDDINTVDDEXTGNDVDDEXTVDDINTVDDEXTVDDEXTVDDINTVDDEXTVDDINTVDDINTDATA0DATA2Ball No.K17K18K19K20P01P02P03P04P17P18P19P20V01V02V03V04V05V06V07V08V09V10V11V12V13V14V15V16V17V18V19V20SignalVDDINTVDDINTGND/ID01DATA16SDA10WRVDDINTVDDINTVDDINTVDDINTDATA8DATA9ADDR22ADDR23VDDINTGNDGNDGNDGNDVDDINTGNDGNDGNDVDDINTVDDEXTGNDVDDINTGNDGNDGNDDATA1DATA3Ball No.L17L18L19L20R01R02R03R04R17R18R19R20W01W02W03W04W05W06W07W08W09W10W11W12W13W14W15W16W17W18W19W20SignalVDDINTVDDINTDATA15DATA14SDWESDRASGNDGNDVDDEXTGNDDATA6DATA7GNDADDR21ADDR19ADDR20ADDR17ADDR16ADDR15ADDR14AVDDAVSSADDR13ADDR12ADDR10ADDR8ADDR5ADDR4ADDR1ADDR2ADDR0NCBall No.M17M18M19M20T01T02T03T04T17T18T19T20Y01Y02Y03Y04Y05Y06Y07Y08Y09Y10Y11Y12Y13Y14Y15Y16Y17Y18Y19Y20SignalVDDEXTGNDDATA12DATA13SDCKESDCASGNDVDDEXTGNDGNDDATA5DATA4GNDNCNC
ADDR18NC/BR11NC/BR21XTAL2CLKINNCNC
NC/BR31NC/BR41ADDR11ADDR9ADDR7ADDR6ADDR3GNDGNDNC
Applies to ADSP-21368 models only.
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ADSP-21367/ADSP-21368/ADSP-21369
Figure43 shows the bottom view of the SBGA ball configura-tion. Figure44 shows the top view of the SBGA ball configuration.
1234567891011121314151617181920ABCDEFGHJ2019181716151413121110987654321ABCDEFGHJKLMNPRTUVWYTOPVIEWBOTTOMVIEWKLMNPRTUVWYKEYVDDINTVDDEXTGNDAVDDAVSSKEYVDDINTI/OSIGNALSVDDEXTGNDAVDDAVSSI/OSIGNALSNOCONNECTNOCONNECTFigure 44.256-Ball SBGA Ball Configuration (Top View)
Figure 43.256-Ball SBGA Ball Configuration (Bottom View)
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ADSP-21367/ADSP-21368/ADSP-21369
208-LEAD MQFP PINOUTTable 47.208-Lead MQFP Pin Assignment (Numerically by Lead Number)
Pin No.1234567891011121314151617181920212223242526272829303132333435363738394041424344
SignalVDDDATA28DATA27GNDVDDEXTDATA26DATA25DATA24DATA23GNDVDDDATA22DATA21DATA20VDDEXTGNDDATA19DATA18VDDGNDDATA17VDDGNDVDDGNDDATA16DATA15DATA14DATA13DATA12VDDEXTGNDVDDGNDDATA11DATA10DATA9DATA8DATA7DATA6VDDEXTGNDVDDDATA4
Pin No.5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
SignalVDDGNDVDDEXTADDR0ADDR2ADDR1ADDR4ADDR3ADDR5GNDVDDGNDVDDEXTADDR6ADDR7ADDR8ADDR9ADDR10GNDVDDGNDVDDEXTADDR11ADDR12ADDR13GNDVDDAVSSAVDDGNDCLKINXTAL2VDDEXTGNDVDDADDR14GNDVDDEXTADDR15ADDR16ADDR17ADDR18GNDVDDEXTPin No.105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148
SignalVDDGNDVDDEXTSDCASSDRASSDCKESDWEWRSDA10GNDVDDEXTSDCLK0GNDVDDRDACKFLAG3FLAG2FLAG1FLAG0DAI20GNDVDDGNDVDDEXTDAI19DAI18DAI17DAI16DAI15DAI14DAI13DAI12VDDVDDEXTGNDVDDGNDDAI11DAI10DAI8DAI9DAI6DAI7
Pin No.157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200
SignalVDDVDDGNDVDDVDDVDDTDITRSTTCKGNDVDDTMS
CLK_CFG0BOOT_CFG0CLK_CFG1EMUBOOT_CFG1TDODAI4DAI2DAI3DAI1VDDEXTGNDVDDGNDDPI14DPI13DPI12DPI11DPI10DPI9DPI8DPI7VDDEXTGNDVDDGNDDPI6DPI5DPI4DPI3DPI1DPI2
Rev. A|Page 52 of 56|August 2006
ADSP-21367/ADSP-21368/ADSP-21369
Table 47.208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued)
Pin No.4546474849505152
SignalDATA5DATA2DATA3DATA0DATA1VDDEXTGNDVDDPin No.979899100101102103104
SignalADDR19ADDR20ADDR21ADDR23ADDR22MS1MS0VDDPin No.149150151152153154155156
SignalDAI5VDDEXTGNDVDDGNDVDDGNDVDDPin No.201202203204205206207208
SignalCLKOUTRESETVDDEXTGNDDATA30DATA31DATA29VDDRev. A|Page 53 of 56|August 2006
ADSP-21367/ADSP-21368/ADSP-21369
PACKAGE DIMENSIONSThe ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball lead-free and leaded SBGA, and 208-lead lead-free MQFP packages.
0.750.600.454.10MAX208130.8530.60SQ30.35157156SEATINGPLANEPIN1INDICATORTOPVIEW(PINSDOWN)28.2028.00SQ27.803.603.403.200.500.25VIEWA0.200.090.08MAX(LEADCOPLANARITY)VIEWAROTATED90°CCW52531051040.50BSC(LEADPITCH)0.270.17(LEADWIDTH)NOTES:1.THEACTUALPOSITIONOFEACHLEADISWITHIN0.08FROMITSIDEALPOSITIONWHENMEASUREDINTHELATERALDIRECTION.2.CENTERDIMENSIONSARENOMINAL.3.DIMENSIONSAREINMILLIMETERSANDCOMPLYWITHJEDECSTANDARDMS-029,FA-1.Figure 45.208-Lead MQFP (S-208-2)
Rev. A|Page 54 of 56|August 2006
ADSP-21367/ADSP-21368/ADSP-21369
A1CORNERINDEXAREA2018161412108642191715131197531A1BALLINDICATORABCDEFGHJKLMNPRTUVWYBOTTOMVIEWTOPVIEW27.00BSCSQDETAILA24.13REFSQ1.27NOM0.700.600.501.000.800.60DETAILA1.70MAX0.10MIN0.20COPLANARITYDIMENSIONSAREINMILLIMETERSANDCOMPLYWITHJEDECSTANDARDSMO-192-BAL-2.BALLDIAMETER0.900.750.600.25MIN4ϫSEATINGPLANEFigure 46.256-Ball SBGA, Thermally Enhanced (BP-256)
SURFACE-MOUNT DESIGN
Table48 is provided as an aide to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard.
Table 48.SBGA Data for Use with Surface-Mount Design
Package
256-Lead Ball Grid Array SBGA (BP-256)
Ball Attach Type
Solder Mask Defined (SMD)
Solder Mask Opening0.63
Ball Pad Size0.73
Rev. A|Page 55 of 56|August 2006
ADSP-21367/ADSP-21368/ADSP-21369
ORDERING GUIDE
Operating VoltagePackage Internal/External Description1.2 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.2 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V1.3 V/3.3 V
208-Lead MQFP256-Ball SBGA256-Ball SBGA256-Ball SBGA256-Ball SBGA256-Ball SBGA256-Ball SBGA256-Ball SBGA256-Ball SBGA208-Lead MQFP256-Ball SBGA256-Ball SBGA256-Ball SBGA256-Ball SBGA
Part Number ADSP-21367KSZ-1A2, 3ADSP-21367KBP-2A3ADSP-21367KBPZ-2A2, 3ADSP-21367BBP-2AADSP-21367BBPZ-2A2ADSP-21368KBP-2AADSP-21368KBPZ-2A2ADSP-21368BBP-2AADSP-21368BBPZ-2A2ADSP-21369KSZ-1A2ADSP-21369KBP-2AADSP-21369KBPZ-2A2ADSP-21369BBP-2AADSP-21369BBPZ-2A212Temperature Range 10°C to +70°C0°C to +70°C0°C to +70°C–40°C to +85°C–40°C to +85°C0°C to +70°C0°C to +70°C–40°C to +85°C–40°C to +85°C0°C to +70°C0°C to +70°C0°C to +70°C–40°C to +85°C–40°C to +85°C
Instruction On-Chip RateSRAM266 MHz333 MHz333 MHz333 MHz333 MHz333 MHz333 MHz333 MHz333 MHz266 MHz333 MHz333 MHz333 MHz333 MHz
2M bit2M bit2M bit2M bit2M bit2M bit2M bit2M bit2M bit2M bit2M bit2M bit2M bit2M bit
ROM6M bit6M bit6M bit6M bit6M bit6M bit6M bit6M bit6M bit6M bit6M bit6M bit6M bit6M bit
Package
OptionS-208-2BP-256BP-256BP-256BP-256BP-256BP-256BP-256BP-256S-208-2BP-256BP-256BP-256BP-256
Referenced temperature is ambient temperature.Z = Pb-free part. 3Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC.
©2006 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D05267-0-8/06(A)
Rev. A|Page 56 of 56|August 2006
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