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AN10778
PCB layout guidelines for NXP MCUs in BGA packages
Rev. 01 — 22 January 2009
Application note
Document information Info Keywords
Content
LPC2220, LPC2292, LPC2364, LPC2368, LPC2458, LPC2468, LPC2470, LPC2478, LPC2880, LPC2888, LPC3130, LPC3131, LPC3151, LPC3152, LPC3153, LPC3154, LPC3180/10, LPC3220, LPC3230, LPC3240, LPC3250, LH79524, LH7A400, LH7A404, TFBGA100, TFBGA144, TFBGA208, TFBGA180, TFBGA296, LFBGA208, BGA256, LFBGA256, LFBGA324, LFBGA320, Layout Guidelines, BGA, PCB, Fan-out
This application note is focused on Printed Circuit Board (PCB) layout issues when using (LF)(TF) BGA packages from the NXP LPC Microcontroller family.
Abstract
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
Revision history Rev
Date
Description
01 20090122 Initial release
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
AN10778_1
© NXP B.V. 2009. All rights reserved.
Application note Rev. 01 — 22 January 2009 2 of 13
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
1. Introduction
The plastic Ball Grid Array (BGA), including Low profile Fine pitch BGA (LFBGA) and Thin profile Fine pitch BGA (TFBGA), packages have become, for many applications, the first choice for designers requiring medium to high pin-count IC packaging. For this
reason many of the LPC Family of Microcontrollers are available in the LFBGA or TFBGA package.
When comparing it to other common alternative packages, such as the Quad Flat Pack (QFP), the (LF)(TF)BGA device has many advantages. Such as: • • • • •
The (LF)(TF)BGA has no easy-to-bend leads that can cause deviation from coplanarity.
The (LF)(TF)BGA is typically 20% to 25% smaller than an equivalently functional QFP.
Resolution and smearing problems with respect to the stencil-print process are less because the pitch is larger, and the apertures are circular.
The self-alignment property of the component results in a large process window for automatic placement.
The (LF) (TF)BGA is compatible with today’s assembly techniques, which means that no adjustments are necessary to standard machines or materials.
1.1 Scope
The scope of this application note is focused on Printed Circuit Board (PCB) layout issues when using (LF)(TF) BGA packages from the NXP LPC Microcontroller family. Including: • •
Recommended footprint patterns for the TFBGA180, TFBGA208, TFBGA296 and LFBGA320 pin packages.
Recommended trace, space and via size for fan-out routing of the TFBGA180, TFBGA208, TFBGA296 and LFBGA320 pin packages
It is recommended that other assembly topics such as the solder paste chemistry, reflow solder profile and solder paste stencil etching, which are affected by all components on the board level assembly and not limited to the Microcontroller BGA alone, be a collaborative effort between the system designer and the assembly contractor.
2. BGA Package Description
A cross section of the typical (LF)(TF)BGA is shown in Fig 1.
Fig 1. (LF)(TF)BGA Cross Section
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 3 of 13
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
This application note applies to BGA packages listed in Table 1.
Table 1.
BGA Packages
NXP Outline Code SOT1018-1 [4] SOT926-1 [2] SOT569-2 [2] SOT570-2 [2] SOT950-1 [2] SOT1019-1 [5] SOT1020-1 [5] SOT1048-1 [1] SOT1021-1 [5] SOT930-1 [2] SOT640-1 [3] SOT824-1 [2]
Outline Dimensions 17 x 17 x 1.35mm 9 x 9 x 0.7mm 12 x 12 x 0.7mm 12 x 12 x 0.8mm 15 x 15 x 0.7mm 14 x 14 x 1.27mm 14 x 14 x 1.25mm 15 x 15 x 0.7mm 17 x 17 x 1.25mm 12 x 12 x 0.7mm 10 x 10 x 0.8mm 13 x 13 x 0.9mm
Ball Pitch 1.0mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.65mm 0.5mm 0.5mm
Ball Diam 0.50mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.40mm 0.30mm 0.30mm
Ball Configuration 16 x 16; full matrix 10 x 10; full matrix 13 x 13; partial matrix 14 x 14; partial matrix 17 x 17; partial matrix 16 x 16; partial matrix 16 x 16; full matrix 18 x 18; partial matrix 20 x 20; partial matrix 17 x 17; partial matrix 18 x 18; partial matrix 24 x 24; partial matrix
Package Name BGA256 TFBGA100 TFBGA144 TFBGA180 TFBGA208 LFBGA208 LFBGA256 TFBGA296 LFBGA324 TFBGA208 TFBGA180 LFBGA320
[1] Reference JEDEC MO-216 [2] Reference JEDEC MO-275 [3] Reference JEDEC MO-195 [4] Reference JEDEC MS-034 [5] Reference JEDEC MO-205
3. BGA Footprints
When building a BGA footprint the number one consideration is ensuring the ball pattern and outline matches the device package. This includes correct orientation of ball A1, matching all ball column x row locations, and the ball-to-ball pitch. Solder joint reliability is also of primary concern. For cost sensitive applications, minimizing the number of PCB layers required to route the BGA is a consideration. The BGA land pattern footprint plays a key role in solder joint reliability, and the number of PCB layers required to route the balls.
3.1 Land Pad Design
The PCB BGA land pads have to be designed to ensure solder joint reliability and provide optimum manufacturability. The two basic types of BGA land pad design are: • •
The Solder mask defined land pad (SMD)
The Non-solder mask defined land pad (NSMD); recommended type for PCB
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 4 of 13
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
3.1.1 Solder mask defined land pad (SMD)
The SMD type of BGA land pad design is characterized by the copper pad being larger than the solder mask opening above this pad. Thus the solder joint area of the land pad is defined by the opening in the solder mask.
3.1.2 Non-solder mask defined land pad (NSMD)
The NSMD type of BGA land pad design is characterized by the copper pad being smaller than the solder mask opening. Thus the solder joint area of the land pad is defined by the size of the land pad. The solder mask clearance around the land pad must be large enough to ensure that no solder mask overlaps the land pad. Typical solder mask to land pad clearance is in the range 0.06 – 0.075mm, depending on the PCB manufacturer’s solder mask alignment tolerance.
Fig 2. Solder mask vs non-solder mask defined land pad
3.2 Recommended BGA Footprint
The NSMD type land pad is recommended for the PCB BGA footprint. In addition to the top surface of the land pad, the reflowed solder paste will wett to the side wall making a mechanically stronger solder joint than the SMD type pad. The smaller NSMD land pad also leaves more space for routing traces between the land pads. It has been shown that matching the solder joint area of the PCB land pad to that on the BGA package substrate equalizes the ball solder joint stress between the BGA package and PCB land pad thereby reducing the chance of a solder joint stress crack. All of the BGA packages referenced in this application note use SMD type pads. The NSMD type pads on the PCB should be approximately 10 - 15% smaller than the SMD pads on the BGA to achieve equalized stress. This difference between the BGA package SMD pad and
recommended PCB NSMD pad for each BGA package is reflected in Table 2. A generic BGA footprint is shown in Fig 3, and the specific dimensions for each BGA package are listed in Table 2.
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 5 of 13
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
Fig 3. Generic BGA Footprint Table 2.
Recommended BGA Footprints
Ball Pitch Ball
diameter
BGA256 TFBGA100 TFBGA144 TFBGA180
1.0 0.8 0.8 0.8
0.50 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.4 0.3 0.3
BGA substrate PCB land pad Solder mask Land diameter diameter 0.45 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.26 n/a 0.25
diameter
17.6 9.6 12.6 12.6 15.6 14.6 14.6 15.6 15.6 17.6 12.4 10.4 13.4 Outline X & Y
Package Name
0.45 [4] 0.6 0.35 [4] 0.5 0.35 [4] 0.5 0.35 [4] 0.5 0.35 [4] 0.5 0.30 [4] 0.42 0.30 [4] 0.42 0.35 [4] [6] 0. 5 0.30 [4] [7] 0. 42 0.30 [4] 0.42 0.25 [5] 0.37 0.25 [5] 0.36 0.25 [5] 0.36
TFBGA208 (SOT950-1) 0.8 LFBGA208 LFBGA256 TFBGA296 TFBGA296 LFBGA324
0.8 0.8 0.8 0.8 0.8
TFBGA208 (SOT930-1) 0.65 TFBGA180 (SOT640-1) 0.5 LFBGA320
0.5
Notes:
[1] All dimensions are in millimeters
[2] All BGA substrate land pads are SMD type [3] All PCB land pads are NSMD type
[4] The recommended solder paste diameter is the same as the PCB land pad [5] The recommended solder paste diameter is 0.02mm larger than the PCB land pad [6] Used for routing 1 trace between land pads [7] Used for routing 2 traces between land pads
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 6 of 13
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
4. Recommended Fan-out Trace / Space guidelines
The small pitch between BGA balls and their matrix arrangement makes it impractical to route all of the BGA balls away from the BGA on a single layer. Fan-out vias (also called escape vias) are required to route the balls to other layers on the PCB. There are several via technologies used on PCB’s. They are: Through-via, Blind via, Buried via, Micro via and In-pad via. Through-vias, where the drilled via hole goes through all layers on the PCB, cost considerably less than Blind, Buried, Micro and In-pad vias. Through-vias are generally larger than the other types of vias as well. All recommended fan-out examples in this application note use the through-via exclusively.
4.1 Recommended 1.0 and 0.8mm pitch BGA via fan-out pattern
For 1mm and 0.8mm pitch BGA’s, the recommended via fan-out pattern centers each via within the space between four adjacent BGA land pads as shown in Fig 4. Generally, a single trace is routed between adjacent BGA land pads, allowing the two outer rows of balls to be routed without a fan-out via. For BGA’s with larger than 0.8mm ball pitch one or two traces may be routed between adjacent BGA land pads, allowing the three outer most rows of balls to be routed without a fan out via. By reducing the BGA land pad, trace width and trace-to-pad space design rules for the 0.8mm ball pitch TFBGA296, two traces may be routed between the BGA land pads. See Table 3 for the layout tool design rules for 1.0 and 0.8mm pitch BGA via fan-out.
Fig 4. 1.0 and 0.8mm pitch BGA Via fan-out pattern
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 7 of 13
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
Table 3. BGA Pitch
1.0 and 0.8mm pitch BGA layout design rules BGA land pad
Pad
Via
Land pad to via space
Between vias
Between Land pads
Trace / space
# of traces Trace /
space
# of traces
Drill size Inner plane / finished layer anti-hole size pad
1.0 0.45 0.55 0.3 / 0.18 0.800 0.2 0.15 1 1.0 0.8 0.8
0.45 0.35 0.30
0.485 0.485 0.485
0.25 / 0.1 0.695 0.24 0.1 2 0.25 / 0.1 0.695 0.25 / 0.1 0.695
0.148 0.105 1 0.173 0.105 1
0.18 1 0.11 2 0.15 1 0.1
2
4.2 Recommended 0.65mm pitch BGA via fan-out pattern
For 0.65mm pitch BGA’s, the recommended via fan-out pattern centers each via within
the space between four adjacent BGA land pads. Instead of placing the vias 0.65mm apart they are placed 1.3mm from each other, skipping every other location, and
staggering them between adjacent rows, as the partial fan-out example is shown in Fig 5. With this pattern the TFGBA208 package can use 0.125mm (0.005”) trace and space design rules. With a single trace routed between adjacent BGA land pads, the two outer rows of balls can be routed without a fan-out via. See Table 4 for the layout tool design rules for 0.65mm pitch BGA via fan-out.
(1) Note: no connect pins on the LPC3152/54
Fig 5. Recommended 0.65mm pitch BGA via fan-out pattern
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 8 of 13
NXP Semiconductors
AN10778
PCB layout guidelines for NXP MCUs in BGA packages
Table 4.
0.65mm pitch BGA layout design rules BGA land pad
Pad
Via
Land pad to Between via space vias
Trace /
space
0.122
0.125
Trace / space 0.125
Between Land pads
# of traces 1
BGA Pitch
Drill size Inner
/ finished plane layer hole size anti-pad 0.2 / 0.05 0.6
0.65 0.25 0.425
4.3 Recommended 0.5mm pitch BGA via fan-out pattern
The pattern of centering the through-via within the four adjacent BGA land pads can not be used with 0.5mm pitch BGA’s. This is due to the smallest through-via pad being too large to fit in the space available between the land pads. With a single trace routed between adjacent BGA land pads, the two outer rows of balls can be routed without a fan-out via. The two inner rows of balls must be routed to vias in the center area of the BGA and escape routed on other layers. An example fan-out of the LFBGA320 package is shown in Fig 6. See Table 5 for the layout tool design rules for 0.5mm pitch BGA via fan-out.
Fig 6. Example fan-out of LFBGA320
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 9 of 13
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AN10778
PCB layout guidelines for NXP MCUs in BGA packages
Table 5. 0.5mm pitch BGA layout design rules BGA land pad
Pad
Via
Land pad to Between via space vias
Trace /
space
Trace / space
Between Land pads
# of traces
BGA Pitch
Drill size Inner
/ finished plane layer hole size anti-pad
0.5 0.25 0.4 0.2 / 0.05 0.6 0.1 0.1 0.08 1
5. Board Cost considerations
PCB cost is affected by many factors, generally increasing in cost as: 1. Overall PCB area increases 2. As the number of layers increases
3. Using in-pad via, blind via, buried via, micro via 4. As the diameter of the through-via decreases 5. As the trace width decreases below 0.125mm (5 mils)
6. As the space between metal features decreases below 0.125mm (5 mils)
Therefore, selecting via size, trace width and spacing for fan-out routing of the BGA
requires a balance between feature size, number of PCB layers and overall board area to get the most economical layout.
5.1 Area Rules
On many boards the design rules for via size, trace width and space for fan-out routing of the BGA may require smaller feature sizes than any other area on the board. If your layout tool is capable of defining multiple rule areas, it may be cost effective to limit the area around the BGA to the smaller feature sizes and use larger vias and larger trace widths and spacing for the balance of the board. In other words if all but the BGA fan-out can use 5 or 6 mil trace and space rules, then limiting 3 or 4 mil trace and space rules to the BGA fan-out area may have only a small cost premium.
5.2 How many PCB layers to fan-out the BGA
Generally one trace is routed between adjacent BGA land pads, enabling the two outer rows of BGA balls to be routed on the same layer as the BGA is mounted on. The next two rows in can be routed on the next signal layer, provided the vias are spaced far
enough apart to allow one trace between them, as is the case for the 1.0mm, 0.8mm and 0.65mm recommended fan-out via patterns in Fig 4 and Fig 5. Each additional BGA row will take one additional PCB layer to fan-out. For example, the TFBGA296 has balls seven rows deep and will take 5 PCB layers to fan-out, including power and ground. Because PCB’s are constructed in even number layers, a PCB using the TFBGA296 package would require a minimum of six layers, including one split power plane and one ground plane.
AN10778_1
Rev. 01 — 22 January 2009
© NXP B.V. 2009. All rights reserved.
Application note 10 of 13
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AN10778
PCB layout guidelines for NXP MCUs in BGA packages
6. BGA Power and Ground
NXP LPC Microcontroller family devices have many power and ground pins. This is due to having multiple power domains, and the potential for large simultaneous switching currents when all 16-bit or 32-bit external data bus outputs change from all low to all
high, or all high to all low, at the same time. It is recommended that the MCU VDD(core) and VDD(IO) power nets and VSSx be distributed on a plane layer of the PCB instead of routed by the thin traces, like those used for carrying other signals. BGA power and ground balls are typically routed to a near by fan-out via the same as any signal. It is recommended that the short trace between the BGA ball and fan-out via be no wider
than 0.15mm (6mils). Although it is common to use a wider trace (0.5mm) to route power and ground from other IC packages (SOIC, QFP, TSOP, etc.), using larger than 0.15mm may begin to act like a heat sink that could adversely affect the solder joint. If a BGA power or ground pin must be routed more than 1mm to get to a fan-out via, the trace should be routed the first 1mm with a <= 0.15mm trace then up sized for the balance of the route. It is recommended that all power and ground vias that tie into a plane do so as a solid 360 degree connection, as shown Fig 7a. This provides a lower inductance connection to the plane and will provide a more solid ground plane throughout the BGA area. Avoid the use of thermal (4-point) connections, as shown in Fig 7b.
a. Direct via connection to the plane Fig 7. Via to plane connection
b. Thermal (4-point) connection to the plane
AN10778_1
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© NXP B.V. 2009. All rights reserved.
Application note 11 of 13
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AN10778
PCB layout guidelines for NXP MCUs in BGA packages
7. Legal information
7.1 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of use of such information.
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
7.2 Disclaimers
General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
7.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are property of their respective owners.
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Application note
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AN10778
PCB layout guidelines for NXP MCUs in BGA packages
8. Contents
1. Introduction.........................................................3 1.1 Scope.................................................................3 2. BGA Package Description..................................3 3. BGA Footprints....................................................4 3.1 Land Pad Design................................................4 3.1.1 Solder mask defined land pad (SMD)................5 3.1.2 Non-solder mask defined land pad (NSMD).......5 3.2 Recommended BGA Footprint...........................5 4. Recommended Fan-out Trace / Space
guidelines.............................................................7 4.1 Recommended 1.0 and 0.8mm pitch BGA via fan-out pattern....................................................7 4.2 Recommended 0.65mm pitch BGA via fan-out pattern................................................................8 4.3 Recommended 0.5mm pitch BGA via fan-out pattern................................................................9 5. Board Cost considerations...............................10 5.1 Area Rules.......................................................10 5.2 How many PCB layers to fan-out the BGA.......10 6. BGA Power and Ground...................................11 7. Legal information..............................................12 7.1 Definitions........................................................12 7.2 Disclaimers.......................................................12 7.3 Trademarks......................................................12 8. Contents.............................................................13
Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'.
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, email to: salesaddresses@nxp.com
Date of release: 22 January 2009
Document identifier: AN10778_1
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