SI7119DN-T1-GE3;中文规格书,Datasheet资料

Vishay Siliconix

P-Channel 200-V (D-S) MOSFET

PRODUCT SUMMARY

VDS (V)- 200

RDS(on) (Ω)1.05 at VGS = - 10 V 1.10 at VGS = - 6.0V

ID (A)- 3.8e- 3.6e

Qg (Typ.)10.6 nC

FEATURES

•Halogen-free According to IEC 61249-2-21

Available

•TrenchFET® Power MOSFET

•Low Thermal Resistance PowerPAK®

Package with Small Size and Low 1.07 mm Profile

•100 % UIS and Rg Tested

PowerPAK 1212-8 APPLICATIONS

•Active Clamp in Intermediate DC/DC Power Supplies

3.30 mm S3.30 mm S 1 2 3 S S G 4 D 8 7 6 5 D D D GBottom ViewDOrdering Information:Si7119DN-T1-E3 (Lead (Pb)-free)Si7119DN-T1-GE3 (Lead (Pb)-free and Halogen-free)P-Channel MOSFETABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

arameter Symbol Limit Unit VDSDrain-Source Voltage - 200

V

VGS± 20Gate-Source Voltage

TC = 25 °C- 3.8e- 3.0eTC = 70 °C

Continuous Drain Current (TJ = 150 °C)ID

TA = 25 °C- 1.2a, bTA = 70 °C- 0.95a, bA

IDM- 5Pulsed Drain Current

TC = 25 °C- 5eISContinuous Source-Drain Diode Current

TA = 25 °C- 3.0a, bIAS5Avalanche Current L = 0.1 mH

EASSingle-Pulse Avalanche Energy 1.25mJ

52TC = 25 °C

33TC = 70 °C

PDMaximum Power DissipationW

TA = 25 °C3.7a, bTA = 70 °C2.4a, b

TJ, TstgOperating Junction and Storage Temperature Range - 50 to 150

°Cc, d260Soldering Recommendations (Peak Temperature)

Notes:

a.Surface Mounted on 1\" x 1\" FR4 board.b.t = 10 s.

c.See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposedcopper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed andis not required to ensure adequate bottom side solder interconnection.

d.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.e.TC = 25 °C.

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THERMAL RESISTANCE RATINGS

arameter Symbol Typical Maximum Unit RthJAt ≤ 10 s2835Maximum Junction-to-Ambienta, b

°C/W

RthJC2.93.8Maximum Junction-to-Case (Drain)Steady State Notes:

a.Surface Mounted on 1\" x 1\" FR4 board.

b.Maximum under Steady State conditions is 81 °C/W.

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

arameter Symbol Test Conditions Min.Typ.Max.Static

Drain-Source Breakdown VoltageVDS Temperature CoefficientVGS(th) Temperature CoefficientGate-Source Threshold VoltageGate-Source Leakage

Zero Gate Voltage Drain CurrentOn-State Drain Currenta

Drain-Source On-State ResistanceaForward TransconductanceaDynamicbInput CapacitanceOutput Capacitance

Reverse Transfer CapacitanceTotal Gate ChargeGate-Source ChargeGate-Drain ChargeGate ResistanceTurn-On Delay TimeRise Time

Turn-Off DelayTimeFall Time

Turn-On Delay TimeRise Time

Turn-Off DelayTimeFall Time

Drain-Source Body Diode CharacteristicsContinuous Source-Drain Diode CurrentPulse Diode Forward CurrentaBody Diode Voltage

Body Diode Reverse Recovery TimeBody Diode Reverse Recovery ChargeReverse Recovery Fall TimeReverse Recovery Rise Time

ISISMVSDtrrQrrtatb

IF = - 4 A, dI/dt = 100 A/µs, TJ = 25 °C

IS = - 1 A

- 0.8662154818

TC = 25 °C

- 5- 5- 1.290270

AVnsnCns

VDSΔVDS/TJΔVGS(th)/TJVGS(th) IGSSIDSSID(on) RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd Rgtd(on) trtd(off) tftd(on) trtd(off) tf

VDD = - 100 V, RL = 100 Ω ID ≅ - 1 A, VGEN = - 10 V, Rg = 1 ΩVDD = - 100 V, RL = 100 Ω ID ≅ - 1 A, VGEN = - 6 V, Rg = 1 Ω

f = 1 MHz

VDS = - 100 V, VGS = - 10 V, ID = - 1 AVDS = - 100 V, VGS = - 6 V, ID = - 1 AVDS = - 50 V, VGS = 0 V, f = 1 MHz

VGS = 0 V, ID = - 250 µA

ID = - 250 µA VDS = VGS, ID = - 250 µA VDS = 0 V, VGS = ± 20 V VDS = - 200 V, VGS = 0 V VDS = - 200 V, VGS = 0 V, TJ = 55 °C

VDS ≥ - 10 V, VGS = - 10 VVGS = - 10 V, ID = - 1 A VGS = - 6 V, ID = - 1 A VDS = - 15 V, ID = - 1 A

- 3

0.860.884666362516.210.62.54.95.3161625169112712

82525402515184220

nsΩ

2516

nCpF

1.051.10

- 2- 200

- 250- 5.5

- 4± 100- 1- 10

VmV/°CVnAµAAΩS

Unit Notes:

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.

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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

6 1.5 5 ID- D ra i n C u r r e n t ( A ) VGS = 10 thru 5 V 4 ID- D r a i n C u r r e n t ( A ) 1.2 0.9 T = 125 °C C 3 0.6 T = 25 °C C 0.3 T = - 55 °C C 2 4 V 1 0 0246810 0.0 02468 VDS - Drain-to-Source Voltage (V)VGS - Gate-to-Source Voltage (V) Output Characteristics1.200 1000 Transfer Characteristics

RD i n - R e s s t a n c e ( Ω)S ( o n ) - O - C a p a i t a n c e ( p F ) C c1.120 800 C iss 600 1.040 VGS = 6 V 0.960 400 0.880 VGS = 10 V 200 C oss C rss 020406080100 0.800 0.00 1.22.43.64.86.0 - Drain Current (A)I D VDS - Drain-to-Source Voltage (V)On-Resistance vs. Drain Current

10 VGS- G a t e - t o - S o u r c e V o l a g e V ) t (I = 1 A D 8 VDS = 50 V 2.0 RD - O n - Resistance S ( o n ) (Normalized)VDS = 100 V 6 VDS = 150 V 4 2.4 I = 1 A D CapacitanceVGS = 10 V 1.6 1.2 VGS = 6 V 2 0.8 0 0.03.46.810.213.617.0 0.4 - 50- 250255075100125150 Q - Total Gate Charge (nC)g T J - Junction Temperature (°C)Gate ChargeOn-Resistance vs. Junction Temperature

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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

100T = 150 °C J 10 ource Current (A)IS- SRDS(on)- Drain-to-Source On-Resistance (Ω)5 4 3 T A = 125 °C 2 1T = 25 °C J 0.11 T A = 25 °C 0 00.010 0.3 0.6 0.9 1.2 1.5 VSD - Source-to-Drain Voltage (V) 246810 VGS - Gate-to-Source Voltage (V)Source-Drain Diode Forward Voltage0.8 100 0.6 80 0.4 ( V ) VGS(th ) I = 250 µA D Po w e r ( W ) 60 On-Resistance vs. Gate-to-Source Voltage

0.2 I = 5 mA D 0.0 40 - 0.2 20 - 0.4 - 50- 2502550751001251500 0.01 10 0.001 0.1 1 Time (s) - Temperature (°C)T J Threshold Voltage

100 Limited by RDS(on)*10 ID- Drain Current (A)Single Pulse Power, Junction-to-Ambient

1 ms 1 10 ms 0.1 100 ms 1 s 10 s DCT = 25 °C A Single Pulse 0.1 100 10 1000VDS- Drain-to-Source Vo ltage (V) * VGS > minimum V at which RDS(on)isspecifiedGS 1 0.01 0.001 Safe Operating Area, Junction-to-Ambient

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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

5 4 ID - Drain Current (A)3 2 1 0 0255075100125150T - Case Temperature (°C)C Current Derating*40 2.0 32 Po w r ) e ( W Po w r ) e ( W 02550751001251501.6 24 1.2 16 0.8 8 0.4 0 0.0 0255075100125150T - Case Temperature (°C)C T - Case Temperature (°C)C Power, Junction-to-Case Power, Junction-to-Ambient

* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases

where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.

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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

1Duty Cycle = 0.5 a v TNo r m l i z e d E f f e c t i e r a n s i e n t Th e r m a l I m p e d a n c e 0.2 0.1 0.10.05 0.02 P DM t 1 t 2 1. Duty Cycle, D = t 1 t 2 Notes: 2. Per Unit Base = R = 65 °C/W thJA (t) 3. T - T = P Z JM A DM thJA Single Pulse 0.01-4 10 -3 10 -2 10 -1 110 Square Wave Pulse Duration (s)4. Surface Mounted 10100 1000 Normalized Thermal Transient Impedance, Junction-to-Ambient1Duty Cycle = 0.5 No r m a l i z e d E f f e c t i v e T r a n s i e n t Th e r m a l I m p e d a n c e 0.2 0.1 0.10.05 0.02 Single Pulse 0.0110 -4 -3 10 -2 10 Square Wave Pulse Duration (s)-1 10 1 Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?74251.www.vishay.com6Document Number: 74251S-83052-Rev. B, 29-Dec-08

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Package InformationVishay SiliconixPowerPAK® 1212-8, (SINGLE/DUAL)Wθ18MD4HE2E4KL1ZD1D22D534D245L1θθθeA1AE3Backside View of Single PadHD2D3(2x)D4HE2E4KLc2E1ENotes:1.Inch will govern2Dimensions exclusive of mold gate burrsDetail Z1D12D5K134bD23.Dimensions exclusive of mold flash and cutting burrsE3Backside View of Dual PadMILLIMETERSDIM.AA1bcDD1D2D3D4D5EE1E2E3E4eKK1HLL1θWMECN: S10-0951-Rev. J, 03-May-10DWG: 58820.350.300.300.060°0.153.202.951.471.75MIN.0.970.000.230.233.202.951.980.48NOM.1.04-0.300.283.303.052.11-0.47 TYP.2.3 TYP.3.303.051.601.850.34 TYP.0.65 BSC0.86 TYP.-0.410.430.13-0.250.125 TYP.-0.510.560.2012°0.360.0140.0120.0120.0020°0.0063.403.151.731.980.1260.1160.0580.069MAX.1.120.050.410.333.403.152.240.89MIN.0.0380.0000.0090.0090.1260.1160.0780.019INCHESNOM.0.041-0.0120.0110.1300.1200.083-0.0185 TYP.0.090 TYP.0.1300.1200.0630.0730.013 TYP.0.026 BSC0.034 TYP.-0.0160.0170.005-0.0100.005 TYP.-0.0200.0220.00812°0.0140.1340.1240.0680.078MAX.0.0440.0020.0160.0130.1340.1240.0880.035

Document Number: 71656Revison: 03-May-10

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PowerPAK® 1212 Mounting and Thermal Considerations

Johnson Zhao

MOSFETs for switching applications are now availablewith die on resistances around 1 mΩ and with thecapability to handle 85 A. While these die capabilitiesrepresent a major advance over what was availablejust a few years ago, it is important for power MOSFETpackaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by thepackage is undesirable. PowerPAK is a new packagetechnology that addresses these issues. The PowerPAK1212-8 provides ultra-low thermal impedance in asmall package that is ideal for space-constrainedapplications. In this application note, the PowerPAK1212-8’s construction is described. Following this,mounting information is presented. Finally, thermaland electrical performance is discussed.

THE PowerPAK PACKAGE

The PowerPAK 1212-8 package (Figure 1) is a deriva-tive of PowerPAK SO-8. It utilizes the same packagingtechnology, maximizing the die area. The bottom of thedie attach pad is exposed to provide a direct, low resis-tance thermal path to the substrate the device ismounted on. The PowerPAK 1212-8 thus translatesthe benefits of the PowerPAK SO-8 into a smallerpackage, with the same level of thermal performance.(Please refer to application note “PowerPAK SO-8Mounting and Thermal Considerations.”)

The PowerPAK 1212-8 has a footprint area compara-ble to TSOP-6. It is over 40 % smaller than standardTSSOP-8. Its die capacity is more than twice the sizeof the standard TSOP-6’s. It has thermal performancean order of magnitude better than the SO-8, and 20times better than TSSOP-8. Its thermal performance isbetter than all current SMT packages in the market. Itwill take the advantage of any PC board heat sinkcapability. Bringing the junction temperature down alsoincreases the die efficiency by around 20 % comparedwith TSSOP-8. For applications where bigger pack-ages are typically required solely for thermal consider-ation, the PowerPAK 1212-8 is a good option.Both the single and dual PowerPAK 1212-8 utilize thesame pin-outs as the single and dual PowerPAK SO-8.The low 1.05 mm PowerPAK height profile makes bothversions an excellent choice for applications withspace constraints.

PowerPAK 1212 SINGLE MOUNTING

To take the advantage of the single PowerPAK 1212-8’sthermal performance see Application Note 826,

Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix MOSFETs. Clickon the PowerPAK 1212-8 single in the index of thisdocument.

In this figure, the drain land pattern is given to make fullcontact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, andtop of the drawn pattern. This extension will serve toincrease the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to thePC board and therefore to the ambient. Note thatincreasing the drain land area beyond a certain pointwill yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditionsof board configuration, copper weight, and layer stack,experiments have found that adding copper beyond anarea of about 0.3 to 0.5 in2 of will yield little improve-ment in thermal performance.

Figure 1. PowerPAK 1212 Devices

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PowerPAK 1212 DUAL

To take the advantage of the dual PowerPAK 1212-8’sthermal performance, the minimum recommendedland pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix MOSFETs. Clickon the PowerPAK 1212-8 dual in the index of this doc-ument.

The gap between the two drain pads is 10 mils. Thismatches the spacing of the two drain pads on the Pow-erPAK 1212-8 dual package.

This land pattern can be extended to the left, right, andtop of the drawn pattern. This extension will serve toincrease the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to thePC board and therefore to the ambient. Note thatincreasing the drain land area beyond a certain pointwill yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditionsof board configuration, copper weight, and layer stack,experiments have found that adding copper beyond anarea of about 0.3 to 0.5 in2 of will yield little improve-ment in thermal performance.

ture profile used, and the temperatures and timeduration, are shown in Figures 2 and 3. For the lead(Pb)-free solder profile, see http://www.vishay.com/doc?73257.

Ramp-Up Rate

Temperature at 155 ± 15 °C Temperature Above 180 °C Maximum Temperature

+ 6 °C /Second Maximum 120 Seconds Maximum 70 - 180 Seconds 240 + 5/- 0 °C

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solderreflow reliability requirements. Devices are subjectedto solder reflow as a preconditioning test and are thenreliability-tested using temperature cycle, bias humid-ity, HAST, or pressure pot. The solder reflow tempera-

Time at Maximum Temperature 20 - 40 Seconds Ramp-Down Rate + 6 °C/Second Maximum

Figure 2. Solder Reflow Temperature Profile

10 s (max)210 - 220 °C3 °C/s (max)183 °C140 - 170 °C50 s (max)3° C/s (max)60 s (min)Pre-Heating ZoneReflow Zone4 °C/s (max)Maximum peak temperature at 240 °C is allowed.Figure 3. Solder Reflow Temperatures and Time Durations

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TABLE 1: EQIVALENT STEADY STATE PERFORMANCE

PackageConfiguration

Thermal Resiatance RthJC(C/W)

20

SO-8Single

Dual40

TSSOP-8Single52

Dual83

TSOP-8Single40

Dual90

PPAK 1212Single2.4

Dual5.5

PPAK SO-8Single1.8

Dual5.5

PowerPAK 121249.8 °CStandard SO-885 °CStandard TSSOP-8149 °CTSOP-6125 °C2.4 °C/WPC Board at 45 °C20 °C/W52 °C/W40 °C/WFigure 4. Temperature of Devices on a PC Board

THERMAL PERFORMANCEIntroduction

A basic measure of a device’s thermal performance isthe junction-to-case thermal resistance, Rθjc, or thejunction to- foot thermal resistance, Rθjf. This parameteris measured for the device mounted to an infinite heatsink and is therefore a characterization of the deviceonly, in other words, independent of the properties of theobject to which the device is mounted. Table 1 shows acomparison of the PowerPAK 1212-8, PowerPAK SO-8,standard TSSOP-8 and SO-8 equivalent steady stateperformance.

By minimizing the junction-to-foot thermal resistance, theMOSFET die temperature is very close to the tempera-ture of the PC board. Consider four devices mounted ona PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junc-tion-to-foot thermal resistance characteristics of thePowerPAK 1212-8 and the other SMT packages, dietemperatures are determined to be 49.8 °C for the Pow-erPAK 1212-8, 85 °C for the standard SO-8, 149 °C forstandard TSSOP-8, and 125 °C for TSOP-6. This is a4.8 °C rise above the board temperature for the Power-PAK 1212-8, and over 40 °C for other SMT packages. A4.8 °C rise has minimal effect on rDS(ON) whereas a riseof over 40 °C will cause an increase in rDS(ON) as highas 20 %.

Spreading Copper

Designers add additional copper, spreading copper, tothe drain pad to aid in conducting heat from a device. Itis helpful to have some information about the thermalperformance for a given area of spreading copper.

Figure 5 and Figure 6 show the thermal resistance of aPowerPAK 1212-8 single and dual devices mounted ona 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-nal layers and the backside layer are solid copper. Theinternal layers were chosen as solid copper to model thelarge power and ground planes common in many appli-cations. The top layer was cut back to a smaller area andat each step junction-to-ambient thermal resistancemeasurements were taken. The results indicate that anarea above 0.2 to 0.3 square inches of spreading coppergives no additional thermal performance improvement.A subsequent experiment was run where the copper onthe back-side was reduced, first to 50 % in stripes tomimic circuit traces, and then totally removed. No signif-icant effect was observed.

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SI7119DN-T1-GE3