AMD-750资料

AMD-750

Chipset Overview

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Publication # 23016Rev: AIssue Date: August 1999

© 1999 Advanced Micro Devices, Inc. All rights reserved.

The contents of this document are provided in connection with AdvancedMicro Devices, Inc. (“AMD”) products. AMD makes no representations orwarranties with respect to the accuracy or completeness of the contents ofthis publication and reserves the right to make changes to specifications andproduct descriptions at any time without notice. No license, whether express,implied, arising by estoppel or otherwise, to any intellectual property rightsis granted by this publication. Except as set forth in AMD’s Standard Termsand Conditions of Sale, AMD assumes no liability whatsoever, and disclaimsany express or implied warranty, relating to its products including, but notlimited to, the implied warranty of merchantability, fitness for a particularpurpose, or infringement of any intellectual property right.

AMD’s products are not designed, intended, authorized or warranted for useas components in systems intended for surgical implant into the body, or inother applications intended to support or sustain life, or in any other applica-tion in which the failure of AMD’s product could create a situation where per-sonal injury, death, or severe property or environmental damage may occur.AMD reserves the right to discontinue or make changes to its products at anytime without notice.

Trademarks

AMD, the AMD logo, AMDAthlon, and combinations thereof, AMD-750, AMD-751, and AMD-756 are trademarksof Advanced Micro Devices, Inc.

Microsoft and Windows are registered trademarks of Microsoft Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks oftheir respective companies.

23016A—August 1999

AMD-750™ Chipset Overview

AMD-750™ Chipset

The AMDAthlon™ processor powers the next generation of computing platforms, delivering the ultimate performance for cutting-edge applications and an unprecedented computing

experience.

The AMD-750™ chipset is a highly integrated system logicsolution that delivers enhanced performance for theAMDAthlon processor and other AMDAthlon frontsidebus-compatible processors. The AMD-750 chipset consists ofthe AMD-751™ system controller in a 492-pin plastic ball-gridarray (PBGA) package and the AMD-756™ peripheral buscontroller.

The AMD-751 system controller features the AMDAthlonfrontside bus, system memory controller, accelerated graphicsport (AGP) controller, and peripheral component interconnect(PCI) bus controller.

The AMD-756 peripheral bus controller features three primaryblocks (PCI-to-ISA bridge, USB controller interface, EIDEUDMA-33 and -66 controller), each with independent access tothe PCI bus, a complete set of PCI interface signals and statemachines, and capable of working independently with separatedevices.

Figure 1 on page 2 shows the block diagram of the AMD-750chipset system.

AMD-750™ Chipset1

AMD-750™ Chipset Overview

23016A—August 1999

AMD Athlon™ProcessorFrontside BusAGP Bus-bitAMD-751™System ControllerSystem Controller

72-bitAGPSDRAMDRAM

Memory Bus-bitSERR#

PREQ#PGNT#WSC#

PCI Bus

32-bitAMD-756™Peripheral Bus SouthbridgeController

System Management,Reset, Initialize,Interrupts

LANEthernetSMBusISA BusSCSI

USBusEIDE Bus

16-bitBIOS

Figure 1.AMD-750™ Chipset System Block Diagram

2AMD-750™ Chipset

23016A—August 1999

AMD-750™ Chipset Overview

AMD-751™ System Controller

Key features of the AMD-751 system controller are provided inthis section. For more information, see the AMD-751™ SystemController Data Sheet, order# 21910.

The AMD-751 system controller is designed with the followingfeatures:

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The AMDAthlon frontside bus supports three 200-MHzhigh-speed channels

The 33-MHz 32-bit PCI 2.2-compliant bus interface supportsup to six masters

The 66-MHz AGP 2.0-compliant interface supports 2x datatransfer mode

High-speed memory—The AMD-751 system controller isdesigned to support 100-MHz PC-100 revision 1.0 SDRAMDIMMs

AMDAthlon™ System Bus

The AMDAthlon frontside bus has the following features:

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High-performance point-to-point system bus topologySource synchronous clocking for high-speed transfers

HSTL-like low-voltage swing transceiver logic signal levelsThree 200-MHz independent high-speed channels:•13-pin processor request channel•13-pin system probe channel

•72-pin data transfer channel (8-bit ECC)

1.6 Gbytes per second peak-data-transfer rates at 200 MHzLarge -byte (cache line) data burst transfersData Buffers:

•Memory write FIFO (MWF) •Memory read FIFO (MRF)

•PCI/APCI (AGP-PCI) write buffer•

PCI/APCI read bufferAMD-751™ System Controller

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AMD-750™ Chipset Overview

23016A—August 1999

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Transaction Queues:

•Command queue (CQ)

•Memory write queue (MWQ) •Memory read queue (MRQ) •Probe (snoop) queue (PQ)

Integrated Memory Controller

The integrated memory controller has the following features:

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Memory Request Organizer (MRO)—Serves as a datacrossbar, determines request dependencies, and optimizesscheduling of memory requests

The AMD-751 system controller supports the followingconcurrences:

•Processor-to-main-memory with PCI-to-main-memory•Processor-to-main-memory with AGP-to-main-memory•Processor-to-PCI with PCI-to-main-memory or AGP-to-main-memory

Memory error correcting code (ECC) supportSupports the following DRAM:

•Up to three non-buffered PC-100 revision 1.0 SDRAMDIMMs using 16-Mbit, -Mbit, and 128-Mbit technology •-bit data width, plus 8-bit ECC paths•Flexible row and column addressingSupports up to 768 Mbytes of memory

Four open pages within one CS (device selected by chipselect) for one quadword

Default two-page leapfrog policy for eight quadwordrequests

BIOS-configurable memory-timing parameters andconfiguration parameters

3.3-V memory interface operation with no external buffersFour cache lines (32 quadwords) of processor-to-DRAMposted write buffers with full read-around capabilityConcurrent DRAM writeback and read-around-write Burst read and write transactions

AMD-751™ System Controller

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23016A—August 1999

AMD-750™ Chipset Overview

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Decoupled and burst DRAM refresh with staggered CStiming

Provides the following refresh options:•Programmable refresh rate•CAS-before-RAS

•Populated banks only

•Chipset powerdown via SDRAM automatic refreshcommand

•Automatic refresh of idle slots—improves busavailability for memory access by the processor orsystem

PCI Bus Controller

The PCI bus controller has the following features:

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Compliance with PCI Local Bus Specification, Revision 2.2Supports six PCI masters

32-bit interface, compatible with 3.3-V and 5-V PCI I/OSynchronous PCI bus operation up to 33 MHzPCI-initiator peer concurrence

Automatic processor-to-PCI burst cycle detection

Four-entry, -bit PCI master (processor or AGP) write FIFOExtensive utilization of FIFOs

Zero wait-state PCI initiator and target burst transfers

PCI-to-DRAM data streaming up to 132 Mbytes per secondEnhanced PCI command optimization, such as memory readline (MRL), memory read multiple (MRM), andmemory-write-and-invalidate (MWI)

Timer-enforced fair arbitration between PCI initiatorsSupports advanced concurrency

Supports retry disconnect for improved bus utilizationPCI read buffer keeps track of each masterPCI target request queue

AMD-751™ System Controller5

AMD-750™ Chipset Overview

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AGP Features

The AGP features include the following:

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Bus Features

•Compliance with AGP 1.0 specification

•Synchronous 66-MHz 1x and 2x data-transfer modes•Multiplexed and demultiplexed transfers•Up to four pipelined grants

•Support of sideband address (SBA) busRequest Queue Features

•Separate read-request and write-request queues

•Reordering of high-priority requests over low-priorityrequests in queue

•Concurrent issuing of requests from both the writequeue and read queue

•Selects next request to optimize bus utilizationTransaction Queues

•Memory-to-AGP and processor-to-AGP transactionqueues

FIFO Features

•16-entry (-bit) AGP-to-memory write FIFO•-entry (-bit) memory-to-AGP read FIFOSecondary PCI Bus Features

•Pipelined burst reads and writes•Extensive utilization of FIFOs

GART (graphics address remapping table) Features•Conventional (two-level) GART scheme

•Eight-entry, fully-associative GART table cache (GTC)•Three fully-associative GART directory caches (GDC)•One 4-entry for PCI

•One 8-entry for the processor•One 16-entry for AGP

6AMD-751™ System Controller

23016A—August 1999

AMD-750™ Chipset Overview

Power Management

The power management features include the following:

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Support for both ACPI and Microsoft® PC 98 powermanagement

AMD-751 system controller supports the following powerstates:

•Processor Halt/Stop-Grant/Sleep states•Power-On-Suspend

AMD-751™ System Controller7

AMD-750™ Chipset Overview

23016A—August 1999

AMD-756™ Peripheral Bus Controller

Key features of the AMD-756 controller are listed in thissection. For more information, see the AMD-756™ PeripheralBus Controller Data Sheet, order# 228.

The AMD-756 contains the following functional units:

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Integrated ISA bus controller

Enhanced master-mode PCI IDE controller with ultraDMA-33/66 supportUSB controller

Keyboard/mouse controllerReal-time clock

PCI-to-ISA Bridge

The AMD-756 controller includes a PC97-compliant PCI-to-ISAbridge with the following features:

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PCI 2.2-compliant interface

Eight-level doubleword buffer between PCI and ISA busesDual cascaded AT-8259-compatible interrupt controllersDual AT-8237-compatible DMA controllersType F DMA transfer support

Support for ISA legacy distributed DMA across the PCI busAT-82-compatible programmable interval timer

Integrated real-time clock w/extended 256-byte CMOS RAMProgrammable ISA bus clock

Fast reset and gate A20 operation

Edge-triggered or level-sensitive interruptsFlash, 2-Mbyte EPROM, BIOS support

Integrated keyboard controller with PS/2 mouse support

8AMD-756™ Peripheral Bus Controller

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AMD-750™ Chipset Overview

Enhanced IDE Controllers

The AMD-756 controller includes enhanced master mode PCIand IDE controllers with the following features:

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Ultra DMA-33/66 support for a primary and secondary dual-drive port

Transfer rates up to 33 Mbytes per second supporting PIOmodes 1–4, multi-word DMA mode-2 drivers, and up to 66Mbytes per second supporting the ultra DMA-66 interfaceSixteen-level doubleword prefetch and write buffersCommands can be interleaved between the two channelsBus master programming interface for compliance withSFF-8038i 1.0 and Microsoft Windows® 95 Full-featured scatter-gather capabilitySupport for ATAPI-compliant devices

Support for PCI-native and ATA-compatibility modesComplete bus mastering software driver support

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Universal Serial Bus Controller

The AMD-756 controller includes a universal serial bus (USB)controller with the following features:

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USB 1.0 and OHCI compliant

Sixteen-level doubleword FIFO for burst PCI bus accessRoot hub and four ports

Integrated physical-layer transceivers with over-currentdetection status on USB inputs

Legacy keyboard and PS/2 mouse support

AMD-756™ Peripheral Bus Controller9

AMD-750™ Chipset Overview

23016A—August 1999

Plug-n-Play Support

The AMD-756 controller supports plug-n-play with thefollowing features:

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PCI interrupts steerable to any of three interrupt channelsMicrosoft Windows 98 and plug-n-play BIOS compliantSerial IRQ compliant

Power Management

The AMD-756 controller includes the following sophisticatedpower management features:

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Supports advanced configuration and power interfacepower management (ACPI 1.0 compliant)

Supports legacy power management (APM 1.2 compliant)Supports soft-off and power-on suspend with hardwareautomatic wakeup

Two general-purpose timers, one system-inactivity timer,and a 24-bit or 32-bit APCI-compliant timer

Dedicated external modem-ring input pin for systemwakeup

Normal, doze, sleep, suspend, and conserve modesEighteen multiplexed general-purpose I/O pins

SMBus implementation for JEDEC-compatible DIMMidentification and on-board device power/thermal controlPrimary and secondary interrupt differentiation forindividual channelsClock throttling control

Multiple internal and external SMI# sources for flexiblepower management

10AMD-756™ Peripheral Bus Controller