Parallel processing of network packets

专利名称：Parallel processing of network packets发明人：Gordon J. Brebner申请号：US13274945申请日：20111017公开号：US08780914B2公开日：20140715

专利附图：

摘要：A packet processing circuit includes a plurality of header extraction circuits, anda scheduling circuit coupled to the plurality of header extraction circuits. The schedulingcircuit is configured to receive one or more requests to extract header data of arespective packet from a data bus having a plurality of data lanes. In response to each

request, the scheduling circuit determines a first subset of the plurality of data lanes thatcontain the respective header specified by the request, and assigns a respective one ofthe plurality of header extraction circuits to extract respective header data from the firstsubset of the plurality of data lanes.

申请人：Gordon J. Brebner

地址：San Jose CA US

国籍：US

代理人：LeRoy D. Maunu,Lois D. Cartier

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