DM9328N资料

DM9328 Dual 8-Bit Shift RegisterOctober 1988

Revised February 2000

DM9328

Dual 8-Bit Shift Register

General Description

The DM9328 is a high speed serial storage element provid-ing 16 bits of storage in the form of two 8-bit registers. Themultifunctional capability of this device is provided by sev-eral features: 1) additional gating is provided at the input toboth shift registers so that the input is easily multiplexedbetween two sources; 2) the clock of each register may beprovided separately or together; 3) both the true and com-plementary outputs are provided from each 8-bit register,and both registers may be master cleared from a commoninput.

Ordering Code:

Order NumberDM9328N

Package Number

N16E

Package Description

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Logic SymbolConnection Diagram

VCC = Pin 16GND = Pin 8

Pin Descriptions

Pin NamesSD0, D1CP

Data Inputs

Clock Pulse Input (Active HIGH)Common (Pin 9)Separate (Pins 7 and 10)

MRQ7Q7Master Reset Input (Active LOW)Last Stage OutputComplementary Output

Description

Data Select Input

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DM9328Functional Description

The two 8-bit shift registers have a common clock input(pin 9) and separate clock inputs (pins 10 and 7). Theclocking of each register is controlled by the OR function ofthe separate and the common clock input. Each register iscomposed of eight clocked RS master/slave flip-flops and anumber of gates. The clock OR gate drives the eight clockinputs of the flip-flops in parallel. When the two clock inputs(the separate and the common) to the OR gate are LOW,the slave latches are steady, but data can enter the masterlatches via the R and S input. During the first LOW-to-HIGH transition of either, or both simultaneously, of the twoclock inputs, the data inputs (R and S) are inhibited so thata later change in input data will not affect the master; thenthe now trapped information in the master is transferred tothe slave. When the transfer is complete, both the masterand the slave are steady as long as either or both clockinputs remain HIGH. During the HIGH-to-LOW transition ofthe last remaining HIGH clock input, the transfer path frommaster to slave is inhibited first, leaving the slave steady inits present state. The data inputs (R and S) are enabled sothat new data can enter the master. Either of the clockinputs can be used as clock inhibit inputs by applying alogic HIGH signal. Each 8-bit shift register has a 2-input

multiplexer in front of the serial data input. The two datainputs D0 and D1 are controlled by the data select input (S)following the Boolean expression:Serial data in: SD = SD0 + SD1

An asynchronous master reset is provided which, whenactivated by a LOW logic level, will clear all 16 stages inde-pendently of any other input signal.

Shift Select Table

INPUTSSLLHH

D0LHXX

D1XXLH

OUTPUTQ7(tn+ 8)

LHLH

H = HIGH Voltage LevelL = LOW Voltage LevelX = Immaterial

n + 8 = indicates state after eight clock pulse

Logic Diagram

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DM9328Absolute Maximum Ratings(Note 1)

Supply VoltageInput Voltage

Operating Free Air Temperature RangeStorage Temperature Range

7V5.5V

0°C to +70°C−65°C to +150°C

Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the “ElectricalCharacteristics” table are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.

Recommended Operating Conditions

SymbolVCCVIHVILIOHIOLTAts (H)ts (L)th (H)th (L)tw (H)tw (L)tw (L)tw (L)tREC

Parameter

Supply Voltage

HIGH Level Input VoltageLOW Level Input VoltageHIGH Level Output CurrentLOW Level Output CurrentFree Air Operating TemperatureSetup Time HIGH or LOWDn to CP

Hold Time HIGH or LOWDn to CP

Clock Pulse Width HIGH or LOW

MR Pulse Width with CP HIGHMR Pulse Width with CP LOWRecovery Time MR to CP02020002525304033Min4.752

0.8−0.41670

Nom5

Max5.25

UnitsVVVmAmA°Cnsnsnsnsnsns

Electrical Characteristics

Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted)SymbolVIVOHVOLIIIIH

Parameter

Input Clamp VoltageHIGH Level Output VoltageLOW Level Output Voltage

Input Current @ Max Input VoltageHIGH Level Input Current

Conditions

VCC = Min, II = −12 mAVCC = Min, IOH = MaxVIL = Max

VCC = Min, IOL = MaxVIH = Min

VCC = Max, VI = 5.5VVCC = Max, VI = 2.4VMR, Dn InputsCP InputsS Inputs

CP (COM) Inputs

IIL

LOW Level Input Current

VCC = Max, VI = 0.4VMR, Dn InputsCP InputsS InputsCP (COM) Input

IOSICC

Short Circuit Output CurrentSupply Current

VCC = Max (Note 3)VCC = Max

−20

−2.4−3.2−4.8−7077

mAmAmA

6080120−1.6

µA

2.4

3.40.2

0.4140

Min

Typ(Note 2)

Max−1.5

UnitsVVVmA

Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time.

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DM9328Switching Characteristics

VCC = +5.0V, TA = +25°C

CL = 15 pF

SymbolfMAXtPLHtPHLtPHL

Parameter

Min

Maximum Shift Right FrequencyPropagation DelayCP to Q7 or Q7

Propagation Delay MR to Q7

20

203550

ns

RL = 400Ω

Max

MHznsUnits

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DM9328 Dual 8-Bit Shift RegisterPhysical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

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